TY  - JOUR
A1  - Stoffel, Dominik
A1  - Kunz, Wolfgang
A1  - Gerber, Stefan
T1  - And/Or reasoning graphs for determining prime implicants in multi-level combinational networks
Y1  - 1997
ER  - 
TY  - JOUR
A1  - Stoffel, Dominik
A1  - Kunz, Wolfgang
T1  - Record & play : a structural fixed point iteration for sequential circuit verification
Y1  - 1997
SN  - 0-8186-8200-0
ER  - 
TY  - BOOK
A1  - Stoffel, Dominik
A1  - Kunz, Wolfgang
T1  - Structural FSM traversal : theory and a practical algorithm
T3  - Preprint / Universität Potsdam, Institut für Informatik
Y1  - 1997
SN  - 0946-7580
VL  - 1997, 05
PB  - Univ. Potsdam
CY  - Potsdam
ER  - 
TY  - JOUR
A1  - Stoffel, Dominik
A1  - Kunz, Wolfgang
T1  - Logic equivalence checking by optimization techniues
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Reddy, S. M.
A1  - Kunz, Wolfgang
A1  - Pradhan, D. K.
T1  - Novel verification framework combining structural and OBDD methods in a synthesis environment
Y1  - 1995
SN  - 0-8186-7213-7
SN  - 0-8186-7214-5
ER  - 
TY  - JOUR
A1  - Pradhan, D. K.
A1  - Chatterjee, M.
A1  - Swarna, M.
A1  - Kunz, Wolfgang
T1  - Implication-based gate-level synthesis for low-power
Y1  - 1996
SN  - 0-7803-3571-6
ER  - 
TY  - JOUR
A1  - Neumann, I.
A1  - Stoffel, Dominik
A1  - Hartje, Hendrik
A1  - Kunz, Wolfgang
T1  - Cell replication and redundancy elimination during placement for cycle time optimization
Y1  - 1999
ER  - 
TY  - JOUR
A1  - Kunz, Wolfgang
A1  - Stoffel, Dominik
A1  - Menon, P.
T1  - Logic optimization and equivalence checking by implication analysis
Y1  - 1997
ER  - 
TY  - JOUR
A1  - Kunz, Wolfgang
A1  - Reddy, S. M.
A1  - Subodh, M.
A1  - Pradhan, D. K.
T1  - Efficient logic verification in a synthesis environment
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Kunz, Wolfgang
A1  - Pradhan, D. K.
T1  - Recursive learning : a new implication technique for efficient solutions to CAD problems : test, verification and optimization
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Kunz, Wolfgang
A1  - Menon, P.
T1  - Multi-level logic optimization by implication analysis
Y1  - 1994
SN  - 0-89791-690-5
SN  - 0-8186-6416-9
SN  - 0-8186-6417-7
ER  - 
TY  - THES
A1  - Kunz, Wolfgang
T1  - Testing techniques in logic synthesis
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Chatterjee, M.
A1  - Pradhan, D. K.
A1  - Kunz, Wolfgang
T1  - ATPG-based Transformations for random-pattern testable logic synthesis
Y1  - 1995
SN  - 0-8186-7213-7
SN  - 0-8186-7214-5
SN  - 0-8186-7215-3
ER  -