TY  - JOUR
A1  - Bobda, Christophe
A1  - Yonga, Franck
A1  - Gebser, Martin
A1  - Ishebabi, Harold
A1  - Schaub, Torsten H.
T1  - High-level synthesis of on-chip multiprocessor architectures based on answer set programming
JF  - Journal of Parallel and Distributed Computing
N2  - We present a system-level synthesis approach for heterogeneous multi-processor on chip, based on Answer Set Programming(ASP). Starting with a high-level description of an application, its timing constraints and the physical constraints of the target device, our goal is to produce the optimal computing infrastructure made of heterogeneous processors, peripherals, memories and communication components. Optimization aims at maximizing speed, while minimizing chip area. Also, a scheduler must be produced that fulfills the real-time requirements of the application. Even though our approach will work for application specific integrated circuits, we have chosen FPGA as target device in this work because of their reconfiguration capabilities which makes it possible to explore several design alternatives. This paper addresses the bottleneck of problem representation size by providing a direct and compact ASP encoding for automatic synthesis that is semantically equivalent to previously established ILP and ASP models. We describe a use-case in which designers specify their applications in C/C++ from which optimum systems can be derived. We demonstrate the superiority of our approach toward existing heuristics and exact methods with synthesis results on a set of realistic case studies. (C) 2018 Elsevier Inc. All rights reserved.
KW  - System design
KW  - Architecture synthesis
KW  - Answer set programming
KW  - Multi-objective optimization
KW  - Technology mapping
KW  - Reconfigurable architecture
Y1  - 2018
U6  - https://doi.org/10.1016/j.jpdc.2018.02.010
SN  - 0743-7315
SN  - 1096-0848
VL  - 117
SP  - 161
EP  - 179
PB  - Elsevier
CY  - San Diego
ER  - 
TY  - JOUR
A1  - Anders, Jakob
A1  - Mefenza, Michael
A1  - Bobda, Christophe
A1  - Yonga, Franck
A1  - Aklah, Zeyad
A1  - Gunn, Kevin
T1  - A hardware/software prototyping system for driving assistance investigations
JF  - Journal of real-time image processing
N2  - A holistic design and verification environment to investigate driving assistance systems is presented, with an emphasis on system-on-chip architectures for video applications. Starting with an executable specification of a driving assistance application, subsequent transformations are performed across different levels of abstraction until the final implementation is achieved. The hardware/software partitioning is facilitated through the integration of OpenCV and SystemC in the same design environment, as well as OpenCV and Linux in the run-time system. We built a rapid prototyping, FPGA-based camera system, which allows designs to be explored and evaluated in realistic conditions. Using lane departure and the corresponding performance speedup, we show that our platform reduces the design time, while improving the verification efforts.
KW  - System on chip
KW  - Prototyping
KW  - Hardware/software system
KW  - Image processing
KW  - Design flow
KW  - Driver assistance
KW  - FPGA
KW  - Hardware acceleration
Y1  - 2016
U6  - https://doi.org/10.1007/s11554-013-0351-4
SN  - 1861-8200
SN  - 1861-8219
VL  - 11
SP  - 559
EP  - 569
PB  - Springer
CY  - Heidelberg
ER  - 
TY  - JOUR
A1  - Ishebabi, Harold
A1  - Bobda, Christophe
T1  - Automated architecture synthesis for parallel programs on FPGA multiprocessor systems
N2  - This paper presents a concept for automated architecture synthesis for adaptive multiprocessors on chip, in particular for Field-Programmable Gate-Array (FPGA) devices. Given a parallel program, the intent is to simultaneously allocate processor resources and the corresponding communication network, and at the same time, to map the parallel application to get an optimum application-specific architecture. This approach builds up on a previously proposed design platform that automates system integration and FPGA synthesis for such architectures. As a result, the overall concept offers an automated design approach from application mapping to system and FPGA configuration. The automated synthesis is based on combinatorial optimization. Automation is possible because a solvable Integer Linear Programming (ILP) model that captures all necessary design trade-off parameters of such systems has been found. Experimental results to study the feasibility of the automated synthesis indicate that problems with sizes that can be encountered in the embedded domain can be readily solved. Results obtained underscore the need for an automated synthesis for design space exploration.
Y1  - 2009
UR  - http://www.sciencedirect.com/science/journal/01419331
U6  - https://doi.org/10.1016/j.micpro.2008.08.009
SN  - 0141-9331
ER  - 
TY  - JOUR
A1  - Bobda, Christophe
T1  - Special issue on ReCoSoC 2007 : editorial
Y1  - 2009
UR  - http://www.sciencedirect.com/science/journal/01419331
U6  - https://doi.org/10.1016/j.micpro.2009.01.001
SN  - 0141-9331
ER  -