TY  - GEN
A1  - Herzog, Benedict
A1  - Hönig, Timo
A1  - Schröder-Preikschat, Wolfgang
A1  - Plauth, Max
A1  - Köhler, Sven
A1  - Polze, Andreas
T1  - Bridging the Gap
BT  - Energy-efficient Execution of Software Workloads on Heterogeneous Hardware Components
T2  - e-Energy '19: Proceedings of the Tenth ACM International Conference on Future Energy Systems
N2  - The recent restructuring of the electricity grid (i.e., smart grid) introduces a number of challenges for today's large-scale computing systems. To operate reliable and efficient, computing systems must adhere not only to technical limits (i.e., thermal constraints) but they must also reduce operating costs, for example, by increasing their energy efficiency. Efforts to improve the energy efficiency, however, are often hampered by inflexible software components that hardly adapt to underlying hardware characteristics. In this paper, we propose an approach to bridge the gap between inflexible software and heterogeneous hardware architectures. Our proposal introduces adaptive software components that dynamically adapt to heterogeneous processing units (i.e., accelerators) during runtime to improve the energy efficiency of computing systems.
Y1  - 2019
SN  - 978-1-4503-6671-7
U6  - https://doi.org/10.1145/3307772.3330176
SP  - 428
EP  - 430
PB  - Association for Computing Machinery
CY  - New York
ER  - 
TY  - GEN
A1  - Plauth, Max
A1  - Sterz, Christoph
A1  - Eberhardt, Felix
A1  - Feinbube, Frank
A1  - Polze, Andreas
T1  - Assessing NUMA performance based on hardware event counters
T2  - IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
N2  - Cost models play an important role for the efficient implementation of software systems. These models can be embedded in operating systems and execution environments to optimize execution at run time. Even though non-uniform memory access (NUMA) architectures are dominating today's server landscape, there is still a lack of parallel cost models that represent NUMA system sufficiently. Therefore, the existing NUMA models are analyzed, and a two-step performance assessment strategy is proposed that incorporates low-level hardware counters as performance indicators. To support the two-step strategy, multiple tools are developed, all accumulating and enriching specific hardware event counter information, to explore, measure, and visualize these low-overhead performance indicators. The tools are showcased and discussed alongside specific experiments in the realm of performance assessment.
KW  - Parallel programming
KW  - Performance analysis
KW  - Memory management
Y1  - 2017
SN  - 978-0-7695-6149-3
U6  - https://doi.org/10.1109/IPDPSW.2017.51
SN  - 2164-7062
SP  - 904
EP  - 913
PB  - Institute of Electrical and Electronics Engineers
CY  - New York
ER  - 
TY  - CHAP
A1  - Kurbel, Karl
A1  - Nowak, Dawid
A1  - Azodi, Amir
A1  - Jaeger, David
A1  - Meinel, Christoph
A1  - Cheng, Feng
A1  - Sapegin, Andrey
A1  - Gawron, Marian
A1  - Morelli, Frank
A1  - Stahl, Lukas
A1  - Kerl, Stefan
A1  - Janz, Mariska
A1  - Hadaya, Abdulmasih
A1  - Ivanov, Ivaylo
A1  - Wiese, Lena
A1  - Neves, Mariana
A1  - Schapranow, Matthieu-Patrick
A1  - Fähnrich, Cindy
A1  - Feinbube, Frank
A1  - Eberhardt, Felix
A1  - Hagen, Wieland
A1  - Plauth, Max
A1  - Herscheid, Lena
A1  - Polze, Andreas
A1  - Barkowsky, Matthias
A1  - Dinger, Henriette
A1  - Faber, Lukas
A1  - Montenegro, Felix
A1  - Czachórski, Tadeusz
A1  - Nycz, Monika
A1  - Nycz, Tomasz
A1  - Baader, Galina
A1  - Besner, Veronika
A1  - Hecht, Sonja
A1  - Schermann, Michael
A1  - Krcmar, Helmut
A1  - Wiradarma, Timur Pratama
A1  - Hentschel, Christian
A1  - Sack, Harald
A1  - Abramowicz, Witold
A1  - Sokolowska, Wioletta
A1  - Hossa, Tymoteusz
A1  - Opalka, Jakub
A1  - Fabisz, Karol
A1  - Kubaczyk, Mateusz
A1  - Cmil, Milena
A1  - Meng, Tianhui
A1  - Dadashnia, Sharam
A1  - Niesen, Tim
A1  - Fettke, Peter
A1  - Loos, Peter
A1  - Perscheid, Cindy
A1  - Schwarz, Christian
A1  - Schmidt, Christopher
A1  - Scholz, Matthias
A1  - Bock, Nikolai
A1  - Piller, Gunther
A1  - Böhm, Klaus
A1  - Norkus, Oliver
A1  - Clark, Brian
A1  - Friedrich, Björn
A1  - Izadpanah, Babak
A1  - Merkel, Florian
A1  - Schweer, Ilias
A1  - Zimak, Alexander
A1  - Sauer, Jürgen
A1  - Fabian, Benjamin
A1  - Tilch, Georg
A1  - Müller, David
A1  - Plöger, Sabrina
A1  - Friedrich, Christoph M.
A1  - Engels, Christoph
A1  - Amirkhanyan, Aragats
A1  - van der Walt, Estée
A1  - Eloff, J. H. P.
A1  - Scheuermann, Bernd
A1  - Weinknecht, Elisa
ED  - Meinel, Christoph
ED  - Polze, Andreas
ED  - Oswald, Gerhard
ED  - Strotmann, Rolf
ED  - Seibold, Ulrich
ED  - Schulzki, Bernhard
T1  - HPI Future SOC Lab
BT  - Proceedings 2015
N2  - Das Future SOC Lab am HPI ist eine Kooperation des Hasso-Plattner-Instituts mit verschiedenen Industriepartnern. Seine Aufgabe ist die Ermöglichung und Förderung des Austausches zwischen Forschungsgemeinschaft und Industrie.
Am Lab wird interessierten Wissenschaftlern eine Infrastruktur von neuester Hard- und Software kostenfrei für Forschungszwecke zur Verfügung gestellt. Dazu zählen teilweise noch nicht am Markt verfügbare Technologien, die im normalen Hochschulbereich in der Regel nicht zu finanzieren wären, bspw. Server mit bis zu 64 Cores und 2 TB Hauptspeicher. Diese Angebote richten sich insbesondere an Wissenschaftler in den Gebieten Informatik und Wirtschaftsinformatik. Einige der Schwerpunkte sind Cloud Computing, Parallelisierung und In-Memory Technologien. 
In diesem Technischen Bericht werden die Ergebnisse der Forschungsprojekte des Jahres 2015 vorgestellt.  Ausgewählte Projekte stellten ihre Ergebnisse am 15. April 2015 und 4. November 2015 im Rahmen der Future SOC Lab Tag Veranstaltungen vor.
KW  - Future SOC Lab
KW  - Forschungsprojekte
KW  - Multicore Architekturen
KW  - In-Memory Technologie
KW  - Cloud Computing
KW  - maschinelles Lernen
KW  - künstliche Intelligenz
Y1  - 2017
U6  - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:517-opus4-102516
ER  -