TY  - JOUR
A1  - Mühlbauer, Felix
A1  - Schröder, Lukas
A1  - Schölzel, Mario
T1  - Handling of transient and permanent faults in dynamically scheduled super-scalar processors
JF  - Microelectronics reliability
N2  - This article describes architectural extensions for a dynamically scheduled processor to enable three different operation modes, ranging from high-performance, to high-reliability. With minor extensions of the control path, the resources of the super-scalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. Furthermore, the online error-correction capabilities are combined with reconfiguration techniques for permanent fault handling. This reconfiguration can take defective components out of operation permanently, and can be triggered on-demand during runtime, depending on the frequency of online corrected faults. A comprehensive fault simulation was carried out in order to evaluate hardware overhead, fault coverage and performance penalties of the proposed approach. Moreover, the impact of the permanent reconfiguration regarding the reliability and performance is investigated.
KW  - Fault tolerance
KW  - Fail-safe
KW  - Dynamically scheduled processor
Y1  - 2017
U6  - https://doi.org/10.1016/j.microrel.2017.11.021
SN  - 0026-2714
VL  - 80
SP  - 176
EP  - 183
PB  - Elsevier
CY  - Oxford
ER  -