TY - GEN A1 - Aranda, Juan A1 - Schölzel, Mario A1 - Mendez, Diego A1 - Carrillo, Henry T1 - An energy consumption model for multiModal wireless sensor networks based on wake-up radio receivers T2 - 2018 IEEE Colombian Conference on Communications and Computing (COLCOM) N2 - Energy consumption is a major concern in Wireless Sensor Networks. A significant waste of energy occurs due to the idle listening and overhearing problems, which are typically avoided by turning off the radio, while no transmission is ongoing. The classical approach for allowing the reception of messages in such situations is to use a low-duty-cycle protocol, and to turn on the radio periodically, which reduces the idle listening problem, but requires timers and usually unnecessary wakeups. A better solution is to turn on the radio only on demand by using a Wake-up Radio Receiver (WuRx). In this paper, an energy model is presented to estimate the energy saving in various multi-hop network topologies under several use cases, when a WuRx is used instead of a classical low-duty-cycling protocol. The presented model also allows for estimating the benefit of various WuRx properties like using addressing or not. KW - Energy efficiency KW - multimodal wireless sensor network KW - low-duty-cycling KW - wake-up radio Y1 - 2018 SN - 978-1-5386-6820-7 U6 - https://doi.org/10.1109/ColComCon.2018.8466728 PB - IEEE CY - New York ER - TY - GEN A1 - Diaz, Sergio A1 - Mendez, Diego A1 - Schölzel, Mario T1 - Dynamic Gallager-Humblet-Spira Algorithm for Wireless Sensor Networks T2 - 2018 IEEE Colombian Conference on Communications and Computing (COLCOM) N2 - The problem of constructing and maintaining a tree topology in a distributed manner is a challenging task in WSNs. This is because the nodes have limited computational and memory resources and the network changes over time. We propose the Dynamic Gallager-Humblet-Spira (D-GHS) algorithm that builds and maintains a minimum spanning tree. To do so, we divide D-GHS into four phases, namely neighbor discovery, tree construction, data collection, and tree maintenance. In the neighbor discovery phase, the nodes collect information about their neighbors and the link quality. In the tree construction, D-GHS finds the minimum spanning tree by executing the Gallager-Humblet-Spira algorithm. In the data collection phase, the sink roots the minimum spanning tree at itself, and each node sends data packets. In the tree maintenance phase, the nodes repair the tree when communication failures occur. The emulation results show that D-GHS reduces the number of control messages and the energy consumption, at the cost of a slight increase in memory size and convergence time. KW - Minimum spanning tree KW - Tree maintenance Y1 - 2018 SN - 978-1-5386-6820-7 PB - IEEE CY - New York ER - TY - GEN A1 - Mühlbauer, Felix A1 - Schröder, Lukas A1 - Skoncej, Patryk A1 - Schölzel, Mario T1 - Handling manufacturing and aging faults with software-based techniques in tiny embedded systems T2 - 18th IEEE Latin American Test Symposium (LATS 2017) N2 - Non-volatile memory area occupies a large portion of the area of a chip in an embedded system. Such memories are prone to manufacturing faults, retention faults, and aging faults. The paper presents a single software based technique that allows for handling all of these fault types in tiny embedded systems without the need for hardware support. This is beneficial for low-cost embedded systems with simple memory architectures. A software infrastructure and a flow are presented that demonstrate how the presented technique is used in general for fault handling right after manufacturing and in-the-field. Moreover, a full implementation is presented for a MSP430 microcontroller, along with a discussion of the performance, overhead, and reliability impacts. Y1 - 2027 SN - 978-1-5386-0415-1 U6 - https://doi.org/10.1109/LATW.2017.7906756 PB - IEEE CY - New York ER - TY - JOUR A1 - Mühlbauer, Felix A1 - Schröder, Lukas A1 - Schölzel, Mario T1 - Handling of transient and permanent faults in dynamically scheduled super-scalar processors JF - Microelectronics reliability N2 - This article describes architectural extensions for a dynamically scheduled processor to enable three different operation modes, ranging from high-performance, to high-reliability. With minor extensions of the control path, the resources of the super-scalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. Furthermore, the online error-correction capabilities are combined with reconfiguration techniques for permanent fault handling. This reconfiguration can take defective components out of operation permanently, and can be triggered on-demand during runtime, depending on the frequency of online corrected faults. A comprehensive fault simulation was carried out in order to evaluate hardware overhead, fault coverage and performance penalties of the proposed approach. Moreover, the impact of the permanent reconfiguration regarding the reliability and performance is investigated. KW - Fault tolerance KW - Fail-safe KW - Dynamically scheduled processor Y1 - 2017 U6 - https://doi.org/10.1016/j.microrel.2017.11.021 SN - 0026-2714 VL - 80 SP - 176 EP - 183 PB - Elsevier CY - Oxford ER - TY - GEN A1 - Mühlbauer, Felix A1 - Schröder, Lukas A1 - Schölzel, Mario T1 - On hardware-based fault-handling in dynamically scheduled processors T2 - 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2017 N2 - This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes the processor-architecture a very good candidate for applications with dynamically changing reliability requirements, e.g. for automotive applications. The paper reports the hardware-overhead for the extensions, and investigates the performance penalties introduced by the fail-safe and fault-tolerant mode. Furthermore, a comprehensive fault simulation was carried out in order to investigate the fault-coverage of the proposed approach. Y1 - 2017 SN - 978-1-5386-0472-4 U6 - https://doi.org/10.1109/DDECS.2017.7934572 SN - 2334-3133 SN - 2473-2117 SP - 201 EP - 206 PB - IEEE CY - New York ER -