TY  - JOUR
A1  - Bhattacharya, M. K.
A1  - Dimitriev, Alexej
A1  - Gössel, Michael
T1  - Zero-aliasing space compresion using a single periodic output and its application to testing of embedded
Y1  - 2000
ER  - 
TY  - JOUR
A1  - Hilscher, Martin
A1  - Braun, Michael
A1  - Richter, Michael
A1  - Leininger, Andreas
A1  - Gössel, Michael
T1  - X-tolerant test data compaction with accelerated shift registers
N2  - Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution.
Y1  - 2009
UR  - http://www.springerlink.com/content/100286
U6  - https://doi.org/10.1007/s10836-009-5107-5
SN  - 0923-8174
ER  - 
TY  - JOUR
A1  - Singh, Adit D.
A1  - Sogomonyan, Egor S.
A1  - Gössel, Michael
A1  - Seuring, Markus
T1  - Testability evaluation of sequential designs incorporating the multi-mode scannable memory element
Y1  - 1999
ER  - 
TY  - JOUR
A1  - Moschanin, Wladimir
A1  - Saposhnikov, Vl. V.
A1  - Saposhnikov, Va. V.
A1  - Gössel, Michael
T1  - Synthesis of self-dual multi-output combinational circuits for on-line Teting
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Hartje, Hendrik
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - Synthesis of code-disjoint combinational circuits
Y1  - 1997
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - Self-parity combinational-circuits for self-testing, concurrent fault-detection and parity scan design
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Dmitriev, Alexej
A1  - Saposhnikov, V. V.
A1  - Saposhnikov, Vl. V.
A1  - Gössel, Michael
T1  - Self-dual sequential circuits for concurrent chechking
Y1  - 1999
SN  - 0-7695-0390-X ; 0-7695-0391-8
ER  - 
TY  - JOUR
A1  - Saposhnikov, Vl. V.
A1  - Dimitriev, Alexej
A1  - Gössel, Michael
A1  - Saposhnikov, Va. V.
T1  - Self-dual parity checking - a new method for on-line testing
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Saposhnikov, Vl. V.
A1  - Moshanin, Vl.
A1  - Saposhnikov, V. V.
A1  - Gössel, Michael
T1  - Self-dual multi output combinational circuits with output data compaction
Y1  - 1997
ER  - 
TY  - JOUR
A1  - Saposhnikov, Vl. V.
A1  - Saposhnikov, V. V.
A1  - Dimitriev, Alexej
A1  - Gössel, Michael
T1  - Self-dual duplication for error detection
Y1  - 1998
ER  -