TY - GEN A1 - Xenikoudakis, Georgios A1 - Ahmed, Mayeesha A1 - Harris, Jacob Colt A1 - Wadleigh, Rachel A1 - Paijmans, Johanna L. A. A1 - Hartmann, Stefanie A1 - Barlow, Axel A1 - Lerner, Heather A1 - Hofreiter, Michael T1 - Ancient DNA reveals twenty million years of aquatic life in beavers T2 - Current biology : CB N2 - Xenikoudakis et al. report a partial mitochondrial genome of the extinct giant beaver Castoroides and estimate the origin of aquatic behavior in beavers to approximately 20 million years. This time estimate coincides with the extinction of terrestrial beavers and raises the question whether the two events had a common cause. Y1 - 2020 U6 - https://doi.org/10.1016/j.cub.2019.12.041 SN - 0960-9822 SN - 1879-0445 VL - 30 IS - 3 SP - R110 EP - R111 PB - Current Biology Ltd. CY - London ER - TY - GEN A1 - Schäpers, Björn A1 - Niemueller, Tim A1 - Lakemeyer, Gerhard A1 - Gebser, Martin A1 - Schaub, Torsten H. T1 - ASP-Based Time-Bounded Planning for Logistics Robots T2 - Twenty-Eighth International Conference on Automated Planning and Scheduling (ICAPS 2018) N2 - Manufacturing industries are undergoing a major paradigm shift towards more autonomy. Automated planning and scheduling then becomes a necessity. The Planning and Execution Competition for Logistics Robots in Simulation held at ICAPS is based on this scenario and provides an interesting testbed. However, the posed problem is challenging as also demonstrated by the somewhat weak results in 2017. The domain requires temporal reasoning and dealing with uncertainty. We propose a novel planning system based on Answer Set Programming and the Clingo solver to tackle these problems and incentivize robot cooperation. Our results show a significant performance improvement, both, in terms of lowering computational requirements and better game metrics. Y1 - 2018 SN - 2334-0835 SN - 2334-0843 SP - 509 EP - 517 PB - ASSOC Association for the Advancement of Artificial Intelligence CY - Palo Alto ER - TY - GEN A1 - Schaub, Torsten H. A1 - Woltran, Stefan T1 - Special issue on answer set programming T2 - Künstliche Intelligenz Y1 - 2018 U6 - https://doi.org/10.1007/s13218-018-0554-8 SN - 0933-1875 SN - 1610-1987 VL - 32 IS - 2-3 SP - 101 EP - 103 PB - Springer CY - Heidelberg ER - TY - GEN A1 - Saint-Dizier, Patrick A1 - Stede, Manfred T1 - Foundations of the language of argumentation T2 - Argument & computation Y1 - 2017 U6 - https://doi.org/10.3233/AAC-170018 SN - 1946-2166 SN - 1946-2174 VL - 8 IS - 2 Special issue SP - 91 EP - 93 PB - IOS Press CY - Amsterdam ER - TY - GEN A1 - Sahlmann, Kristina A1 - Schwotzer, Thomas T1 - Ontology-based virtual IoT devices for edge computing T2 - Proceedings of the 8th International Conference on the Internet of Things N2 - An IoT network may consist of hundreds heterogeneous devices. Some of them may be constrained in terms of memory, power, processing and network capacity. Manual network and service management of IoT devices are challenging. We propose a usage of an ontology for the IoT device descriptions enabling automatic network management as well as service discovery and aggregation. Our IoT architecture approach ensures interoperability using existing standards, i.e. MQTT protocol and SemanticWeb technologies. We herein introduce virtual IoT devices and their semantic framework deployed at the edge of network. As a result, virtual devices are enabled to aggregate capabilities of IoT devices, derive new services by inference, delegate requests/responses and generate events. Furthermore, they can collect and pre-process sensor data. These tasks on the edge computing overcome the shortcomings of the cloud usage regarding siloization, network bandwidth, latency and speed. We validate our proposition by implementing a virtual device on a Raspberry Pi. KW - Internet of Things KW - Edge Computing KW - oneM2M Ontology KW - M2M KW - Semantic Interoperability KW - MQTT Y1 - 2018 SN - 978-1-4503-6564-2 U6 - https://doi.org/10.1145/3277593.3277597 SP - 1 EP - 7 PB - Association for Computing Machinery CY - New York ER - TY - GEN A1 - Przybylla, Mareen T1 - Interactive objects in physical computing and their role in the learning process T2 - Constructivist foundations N2 - The target article discusses the question of how educational makerspaces can become places supportive of knowledge construction. This question is too often neglected by people who run makerspaces, as they mostly explain how to use different tools and focus on the creation of a product. In makerspaces, often pupils also engage in physical computing activities and thus in the creation of interactive artifacts containing embedded systems, such as smart shoes or wristbands, plant monitoring systems or drink mixing machines. This offers the opportunity to reflect on teaching physical computing in computer science education, where similarly often the creation of the product is so strongly focused upon that the reflection of the learning process is pushed into the background. Y1 - 2019 SN - 1782-348X VL - 14 IS - 3 SP - 264 EP - 266 PB - Vrije Univ. CY - Bussels ER - TY - GEN A1 - Patil, Kaustubh R. A1 - Haider, Peter A1 - Pope, Phillip B. A1 - Turnbaugh, Peter J. A1 - Morrison, Mark A1 - Scheffer, Tobias A1 - McHardy, Alice C. T1 - Taxonomic metagenome sequence assignment with structured output models T2 - Nature methods : techniques for life scientists and chemists Y1 - 2011 U6 - https://doi.org/10.1038/nmeth0311-191 SN - 1548-7091 VL - 8 IS - 3 SP - 191 EP - 192 PB - Nature Publ. Group CY - London ER - TY - GEN A1 - Neubauer, Kai A1 - Haubelt, Christian A1 - Wanko, Philipp A1 - Schaub, Torsten H. T1 - Utilizing quad-trees for efficient design space exploration with partial assignment evaluation T2 - 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) N2 - Recently, it has been shown that constraint-based symbolic solving techniques offer an efficient way for deciding binding and routing options in order to obtain a feasible system level implementation. In combination with various background theories, a feasibility analysis of the resulting system may already be performed on partial solutions. That is, infeasible subsets of mapping and routing options can be pruned early in the decision process, which fastens the solving accordingly. However, allowing a proper design space exploration including multi-objective optimization also requires an efficient structure for storing and managing non-dominated solutions. In this work, we propose and study the usage of the Quad-Tree data structure in the context of partial assignment evaluation during system synthesis. Out experiments show that unnecessary dominance checks can be avoided, which indicates a preference of Quad-Trees over a commonly used list-based implementation for large combinatorial optimization problems. Y1 - 2018 SN - 978-1-5090-0602-1 U6 - https://doi.org/10.1109/ASPDAC.2018.8297362 SN - 2153-6961 SP - 434 EP - 439 PB - IEEE CY - New York ER - TY - GEN A1 - Mühlbauer, Felix A1 - Schröder, Lukas A1 - Skoncej, Patryk A1 - Schölzel, Mario T1 - Handling manufacturing and aging faults with software-based techniques in tiny embedded systems T2 - 18th IEEE Latin American Test Symposium (LATS 2017) N2 - Non-volatile memory area occupies a large portion of the area of a chip in an embedded system. Such memories are prone to manufacturing faults, retention faults, and aging faults. The paper presents a single software based technique that allows for handling all of these fault types in tiny embedded systems without the need for hardware support. This is beneficial for low-cost embedded systems with simple memory architectures. A software infrastructure and a flow are presented that demonstrate how the presented technique is used in general for fault handling right after manufacturing and in-the-field. Moreover, a full implementation is presented for a MSP430 microcontroller, along with a discussion of the performance, overhead, and reliability impacts. Y1 - 2027 SN - 978-1-5386-0415-1 U6 - https://doi.org/10.1109/LATW.2017.7906756 PB - IEEE CY - New York ER - TY - GEN A1 - Mühlbauer, Felix A1 - Schröder, Lukas A1 - Schölzel, Mario T1 - On hardware-based fault-handling in dynamically scheduled processors T2 - 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2017 N2 - This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes the processor-architecture a very good candidate for applications with dynamically changing reliability requirements, e.g. for automotive applications. The paper reports the hardware-overhead for the extensions, and investigates the performance penalties introduced by the fail-safe and fault-tolerant mode. Furthermore, a comprehensive fault simulation was carried out in order to investigate the fault-coverage of the proposed approach. Y1 - 2017 SN - 978-1-5386-0472-4 U6 - https://doi.org/10.1109/DDECS.2017.7934572 SN - 2334-3133 SN - 2473-2117 SP - 201 EP - 206 PB - IEEE CY - New York ER -