TY  - JOUR
A1  - Chen, Junchao
A1  - Lange, Thomas
A1  - Andjelkovic, Marko
A1  - Simevski, Aleksandar
A1  - Lu, Li
A1  - Krstic, Milos
T1  - Solar particle event and single event upset prediction from SRAM-based monitor and supervised machine learning
JF  - IEEE transactions on emerging topics in computing / IEEE Computer Society, Institute of Electrical and Electronics Engineers
N2  - The intensity of cosmic radiation may differ over five orders of magnitude within a few hours or days during the Solar Particle Events (SPEs), thus increasing for several orders of magnitude the probability of Single Event Upsets (SEUs) in space-borne electronic systems. Therefore, it is vital to enable the early detection of the SEU rate changes in order to ensure timely activation of dynamic radiation hardening measures. In this paper, an embedded approach for the prediction of SPEs and SRAM SEU rate is presented. The proposed solution combines the real-time SRAM-based SEU monitor, the offline-trained machine learning model and online learning algorithm for the prediction. With respect to the state-of-the-art, our solution brings the following benefits: (1) Use of existing on-chip data storage SRAM as a particle detector, thus minimizing the hardware and power overhead, (2) Prediction of SRAM SEU rate one hour in advance, with the fine-grained hourly tracking of SEU variations during SPEs as well as under normal conditions, (3) Online optimization of the prediction model for enhancing the prediction accuracy during run-time, (4) Negligible cost of hardware accelerator design for the implementation of selected machine learning model and online learning algorithm. The proposed design is intended for a highly dependable and self-adaptive multiprocessing system employed in space applications, allowing to trigger the radiation mitigation mechanisms before the onset of high radiation levels.
KW  - Machine learning
KW  - Single event upsets
KW  - Random access memory
KW  - monitoring
KW  - machine learning algorithms
KW  - predictive models
KW  - space missions
KW  - solar particle event
KW  - single event upset
KW  - machine learning
KW  - online learning
KW  - hardware accelerator
KW  - reliability
KW  - self-adaptive multiprocessing system
Y1  - 2022
U6  - https://doi.org/10.1109/TETC.2022.3147376
SN  - 2168-6750
VL  - 10
IS  - 2
SP  - 564
EP  - 580
PB  - Institute of Electrical and Electronics Engineers
CY  - [New York, NY]
ER  - 
TY  - JOUR
A1  - Li, Yuanqing
A1  - Breitenreiter, Anselm
A1  - Andjelkovic, Marko
A1  - Chen, Junchao
A1  - Babic, Milan
A1  - Krstić, Miloš
T1  - Double cell upsets mitigation through triple modular redundancy
JF  - Microelectronics Journal
N2  - A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.
KW  - Triple modular redundancy (TMR)
KW  - Double cell upsets (DCUs)
Y1  - 2019
U6  - https://doi.org/10.1016/j.mejo.2019.104683
SN  - 0026-2692
SN  - 1879-2391
VL  - 96
PB  - Elsevier
CY  - Oxford
ER  - 
TY  - JOUR
A1  - Schrape, Oliver
A1  - Andjelkovic, Marko
A1  - Breitenreiter, Anselm
A1  - Zeidler, Steffen
A1  - Balashov, Alexey
A1  - Krstić, Miloš
T1  - Design and evaluation of radiation-hardened standard cell flip-flops
JF  - IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers
N2  - Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant.
KW  - Single event effect
KW  - fault tolerance
KW  - triple modular redundancy
KW  - ASIC
KW  - design flow
KW  - radhard design
Y1  - 2021
U6  - https://doi.org/10.1109/TCSI.2021.3109080
SN  - 1549-8328
SN  - 1558-0806
SN  - 1057-7122
VL  - 68
IS  - 11
SP  - 4796
EP  - 4809
PB  - Inst. of Electr. and Electronics Engineers
CY  - New York, NY
ER  -