TY  - GEN
A1  - Tala, Mahdi
A1  - Schrape, Oliver
A1  - Krstić, Miloš
A1  - Bertozzi, Davide
T1  - Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip
T2  - XXXIII Conference on Design of Circuits and Integrated Systems (DCIS)
N2  - The relentless improvement of silicon photonics is making optical interconnects and networks appealing for use in miniaturized systems, where electrical interconnects cannot keep up with the growing levels of core integration due to bandwidth density and power efficiency limitations. At the same time, solutions such as 3D stacking or 2.5D integration open the door to a fully dedicated process optimization for the photonic die. However, an architecture-level integration challenge arises between the electronic network and the optical one in such tightly-integrated parallel systems. It consists of adapting signaling rates, matching the different levels of communication parallelism, handling cross-domain flow control, addressing re-synchronization concerns, and avoiding protocol-dependent deadlock. The associated energy and performance overhead may offset the inherent benefits of the emerging technology itself. This paper explores a hybrid CMOS-ECL bridge architecture between 3D-stacked technology-heterogeneous networks-on-chip (NoCs). The different ways of overcoming the serialization challenge (i.e., through an improvement of the signaling rate and/or through space-/wavelength division multiplexing options) give rise to a configuration space that the paper explores, in search for the most energy-efficient configuration for high-performance.
Y1  - 2018
SN  - 978-1-7281-0171-2
U6  - https://doi.org/10.1109/DCIS.2018.8681461
SN  - 2471-6170
SN  - 2640-5563
PB  - IEEE
CY  - New York
ER  - 
TY  - GEN
A1  - Schrape, Oliver
A1  - Balashov, Alexey
A1  - Simevski, Aleksandar
A1  - Benito, Carlos
A1  - Krstić, Miloš
T1  - Master-Clone placement with individual clock tree implementation
BT  - a Case on Physical Chip Design
T2  - 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
N2  - A hybrid design approach of the hierarchical physical implementation design flow is presented and demonstrated on a fault-tolerant low-power multiprocessor system. The proposed flow allows to implement selected submodules in parallel with contrary requirements such as identical placement and individual block implementation. The overall system contains four Leon2 cores and communicates via the Waterbear framework and supports Adaptive Voltage Scaling (AVS) functionality. Three of the processor core variants are derived from the first baseline reference core but implemented individually at block level based on their clock tree specification. The chip is prepared for space applications and designed with triple modular redundancy (TMR) for control parts. The low-power performance is enabled by contemporary power and clock management control. An ASIC is fabricated in a low-power 0.13 mu m BiCMOS technology process node.
KW  - Hierarchical Design
KW  - Physical Implementation
KW  - Clock Tree Implementation
Y1  - 2018
SN  - 978-1-5386-7656-1
PB  - IEEE
CY  - New York
ER  - 
TY  - JOUR
A1  - Li, Yuanqing
A1  - Chen, Li
A1  - Nofal, Issam
A1  - Chen, Mo
A1  - Wang, Haibin
A1  - Liu, Rui
A1  - Chen, Qingyu
A1  - Krstić, Miloš
A1  - Shi, Shuting
A1  - Guo, Gang
A1  - Baeg, Sang H.
A1  - Wen, Shi-Jie
A1  - Wong, Richard
T1  - Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree
JF  - Microelectronics reliability
N2  - The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.
KW  - Clock tree
KW  - Modeling
KW  - Single-event transient (SET)
Y1  - 2018
U6  - https://doi.org/10.1016/j.microrel.2018.05.016
SN  - 0026-2714
VL  - 87
SP  - 24
EP  - 32
PB  - Elsevier
CY  - Oxford
ER  - 
TY  - GEN
A1  - Krstić, Miloš
A1  - Jentzsch, Anne-Kristin
T1  - Reliability, safety and security of the electronics in automated driving vehicles - joint lab lecturing approach
T2  - 2018 12TH European Workshop on Microelectronics Education (EWME)
N2  - This paper proposes an education approach for master and bachelor students to enhance their skills in the area of reliability, safety and security of the electronic components in automated driving. The approach is based on the active synergetic work of research institutes, academia and industry in the frame of joint lab. As an example, the jointly organized summer school with the respective focus is organized and elaborated.
KW  - reliability
KW  - safety
KW  - security
KW  - automated driving
KW  - joint lab
Y1  - 2018
SN  - 978-1-5386-1157-9
SP  - 21
EP  - 22
PB  - IEEE
CY  - New York
ER  -