Dokument-ID Dokumenttyp Verfasser/Autoren Herausgeber Haupttitel Abstract Auflage Verlagsort Verlag Erscheinungsjahr Seitenzahl Schriftenreihe Titel Schriftenreihe Bandzahl ISBN Quelle der Hochschulschrift Konferenzname Quelle:Titel Quelle:Jahrgang Quelle:Heftnummer Quelle:Erste Seite Quelle:Letzte Seite URN DOI Abteilungen OPUS4-60676 Wissenschaftlicher Artikel Schrape, Oliver; Andjelkovic, Marko; Breitenreiter, Anselm; Zeidler, Steffen; Balashov, Alexey; Krstić, Miloš Design and evaluation of radiation-hardened standard cell flip-flops Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant. New York, NY Inst. of Electr. and Electronics Engineers 2021 14 IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers 68 11 4796 4809 10.1109/TCSI.2021.3109080 Institut für Informatik und Computational Science OPUS4-61774 Wissenschaftlicher Artikel Breitenreiter, Anselm; Andjelković, Marko; Schrape, Oliver; Krstić, Miloš Fast error propagation probability estimates by answer set programming and approximate model counting We present a method employing Answer Set Programming in combination with Approximate Model Counting for fast and accurate calculation of error propagation probabilities in digital circuits. By an efficient problem encoding, we achieve an input data format similar to a Verilog netlist so that extensive preprocessing is avoided. By a tight interconnection of our application with the underlying solver, we avoid iterating over fault sites and reduce calls to the solver. Several circuits were analyzed with varying numbers of considered cycles and different degrees of approximation. Our experiments show, that the runtime can be reduced by approximation by a factor of 91, whereas the error compared to the exact result is below 1%. Piscataway Inst. of Electr. and Electronics Engineers 2022 12 IEEE Access 10 51814 51825 10.1109/ACCESS.2022.3174564 Institut für Informatik und Computational Science OPUS4-48440 Wissenschaftlicher Artikel Kucharski, Maciej; Ergintav, Arzu; Ahmad, Wael Abdullah; Krstić, Miloš; Ng, Herman Jalli; Kissinger, Dietmar A Scalable 79-GHz Radar Platform Based on Single-Channel Transceivers This paper presents a scalable E-band radar platform based on single-channel fully integrated transceivers (TRX) manufactured using 130-nm silicon-germanium (SiGe) BiCMOS technology. The TRX is suitable for flexible radar systems exploiting massive multiple-input-multipleoutput (MIMO) techniques for multidimensional sensing. A fully integrated fractional-N phase-locked loop (PLL) comprising a 39.5-GHz voltage-controlled oscillator is used to generate wideband frequency-modulated continuous-wave (FMCW) chirp for E-band radar front ends. The TRX is equipped with a vector modulator (VM) for high-speed carrier modulation and beam-forming techniques. A single TRX achieves 19.2-dBm maximum output power and 27.5-dB total conversion gain with input-referred 1-dB compression point of -10 dBm. It consumes 220 mA from 3.3-V supply and occupies 3.96 mm(2) silicon area. A two-channel radar platform based on full-custom TRXs and PLL was fabricated to demonstrate high-precision and high-resolution FMCW sensing. The radar enables up to 10-GHz frequency ramp generation in 74-84-GHz range, which results in 1.5-cm spatial resolution. Due to high output power, thus high signal-to-noise ratio (SNR), a ranging precision of 7.5 mu m for a target at 2 m was achieved. The proposed architecture supports scalable multichannel applications for automotive FMCW using a single local oscillator (LO). Piscataway Inst. of Electr. and Electronics Engineers 2019 15 IEEE Transactions on Microwave Theory and Techniques 67 9 3882 3896 10.1109/TMTT.2019.2914104 Institut für Mathematik OPUS4-54017 misc Tala, Mahdi; Schrape, Oliver; Krstić, Miloš; Bertozzi, Davide Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip The relentless improvement of silicon photonics is making optical interconnects and networks appealing for use in miniaturized systems, where electrical interconnects cannot keep up with the growing levels of core integration due to bandwidth density and power efficiency limitations. At the same time, solutions such as 3D stacking or 2.5D integration open the door to a fully dedicated process optimization for the photonic die. However, an architecture-level integration challenge arises between the electronic network and the optical one in such tightly-integrated parallel systems. It consists of adapting signaling rates, matching the different levels of communication parallelism, handling cross-domain flow control, addressing re-synchronization concerns, and avoiding protocol-dependent deadlock. The associated energy and performance overhead may offset the inherent benefits of the emerging technology itself. This paper explores a hybrid CMOS-ECL bridge architecture between 3D-stacked technology-heterogeneous networks-on-chip (NoCs). The different ways of overcoming the serialization challenge (i.e., through an improvement of the signaling rate and/or through space-/wavelength division multiplexing options) give rise to a configuration space that the paper explores, in search for the most energy-efficient configuration for high-performance. New York IEEE 2018 6 XXXIII Conference on Design of Circuits and Integrated Systems (DCIS) 978-1-7281-0171-2 10.1109/DCIS.2018.8681461 Hasso-Plattner-Institut für Digital Engineering GmbH OPUS4-45860 Wissenschaftlicher Artikel Krstić, Miloš; Weidling, Stefan; Petrovic, Vladimir; Sogomonyan, Egor S. Enhanced architectures for soft error detection and correction in combinational and sequential circuits In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master-slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26-28% lower than the TMR. (C) 2015 Elsevier Ltd. All rights reserved. Oxford Elsevier 2016 9 Microelectronics reliability 56 212 220 10.1016/j.microrel.2015.10.022 OPUS4-52394 Wissenschaftlicher Artikel Li, Yuanqing; Chen, Li; Nofal, Issam; Chen, Mo; Wang, Haibin; Liu, Rui; Chen, Qingyu; Krstić, Miloš; Shi, Shuting; Guo, Gang; Baeg, Sang H.; Wen, Shi-Jie; Wong, Richard Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method. Oxford Elsevier 2018 9 Microelectronics reliability 87 24 32 10.1016/j.microrel.2018.05.016 Institut für Informatik und Computational Science OPUS4-42722 Wissenschaftlicher Artikel Fan, Xin; Stegmann, Mikkel B.; Schrappe, Oliver; Zeidler, Steffen; Jensen, Isac G.; Thorsen, Jannich; Bjerregaard, Tobias; Krstić, Miloš Frequency-domain optimization of digital switching noise based on clock scheduling The simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in terms of noise power, a two-phase clocking scheme is employed for system timing. Second, on-chip clock latencies are manipulated to target harmonic peaks in specific frequency bands for the spectral noise optimization. An automated design flow, which allows for noise optimization in user-defined application-specific frequency bands, is developed. The effectiveness of our design solution is validated by measurements of substrate noise and conductive EMI (electromagnetic interference) noise on a test chip, which consists of four wireless sensor node baseband processors each addressing a distinct clock-tree-synthesis strategy. Compared to the reference synchronous design, the proposed clock scheduling solution substantially reduces noise in the target GSM-850 band, i.e., by 11.1 dB on the substrate noise and 12.9 dB on the EMI noise, along with dramatic noise peak drops measured at the 50-MHz clock frequency. 11 IEEE Transactions on Circuits and Systems I 63 7 982 993 10.1109/TCSI.2016.2546118 Institut für Physik und Astronomie OPUS4-42723 Wissenschaftlicher Artikel Krstić, Miloš; Weidling, Stefan; Petrovic, Vladimir; Sogomonyan, Egor S. Enhanced architectures for soft error detection and correction in combinational and sequential circuits In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master-slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26-28% lower than the TMR. 8 Microelectronics Reliability 56 212 220 Institut für Informatik und Computational Science OPUS4-59201 Wissenschaftlicher Artikel Dug, Mehmed; Weidling, Stefan; Sogomonyan, Egor; Jokic, Dejan; Krstić, Miloš Full error detection and correction method applied on pipelined structure using two approaches In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach. Singapore World Scientific 2020 15 Journal of circuits, systems and computers 29 13 10.1142/S0218126620502187 Institut für Informatik und Computational Science OPUS4-58624 Wissenschaftlicher Artikel Kuentzer, Felipe A.; Krstić, Miloš Soft error detection and correction architecture for asynchronous bundled data designs In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6% to 17.6%, and increasing energy efficiency, which can be up to 6.5%. New York Institute of Electrical and Electronics Engineers 2020 12 IEEE transactions on circuits and systems 67 12 4883 4894 10.1109/TCSI.2020.2998911 Institut für Informatik und Computational Science OPUS4-57623 Wissenschaftlicher Artikel Chen, Junchao; Lange, Thomas; Andjelkovic, Milos; Simevski, Aleksandar; Krstić, Miloš Prediction of solar particle events with SRAM-based soft error rate monitor and supervised machine learning This work introduces an embedded approach for the prediction of Solar Particle Events (SPEs) in space applications by combining the real-time Soft Error Rate (SER) measurement with SRAM-based detector and the offline trained machine learning model. The proposed approach is intended for the self-adaptive fault-tolerant multiprocessing systems employed in space applications. With respect to the state-of-the-art, our solution allows for predicting the SER 1 h in advance and fine-grained hourly tracking of SER variations during SPEs as well as under normal conditions. Therefore, the target system can activate the appropriate mechanisms for radiation hardening before the onset of high radiation levels. Based on the comparison of five different machine learning algorithms trained with the public space flux database, the preliminary results indicate that the best prediction accuracy is achieved with the recurrent neural network (RNN) with long short-term memory (LSTM). Oxford Elsevier 2020 6 Microelectronics reliability 114 10.1016/j.microrel.2020.113799 Institut für Physik und Astronomie OPUS4-54060 misc Schrape, Oliver; Balashov, Alexey; Simevski, Aleksandar; Benito, Carlos; Krstić, Miloš Master-Clone placement with individual clock tree implementation A hybrid design approach of the hierarchical physical implementation design flow is presented and demonstrated on a fault-tolerant low-power multiprocessor system. The proposed flow allows to implement selected submodules in parallel with contrary requirements such as identical placement and individual block implementation. The overall system contains four Leon2 cores and communicates via the Waterbear framework and supports Adaptive Voltage Scaling (AVS) functionality. Three of the processor core variants are derived from the first baseline reference core but implemented individually at block level based on their clock tree specification. The chip is prepared for space applications and designed with triple modular redundancy (TMR) for control parts. The low-power performance is enabled by contemporary power and clock management control. An ASIC is fabricated in a low-power 0.13 mu m BiCMOS technology process node. New York IEEE 2018 4 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) 978-1-5386-7656-1 Institut für Physik und Astronomie OPUS4-54104 misc Andjelkovic, Marko; Babic, Milan; Li, Yuanqing; Schrape, Oliver; Krstić, Miloš; Kraemer, Rolf Use of decoupling cells for mitigation of SET effects in CMOS combinational gates This paper investigates the applicability of CMOS decoupling cells for mitigating the Single Event Transient (SET) effects in standard combinational gates. The concept is based on the insertion of two decoupling cells between the gate's output and the power/ground terminals. To verify the proposed hardening approach, extensive SPICE simulations have been performed with standard combinational cells designed in IHP's 130 nm bulk CMOS technology. Obtained simulation results have shown that the insertion of decoupling cells results in the increase of the gate's critical charge, thus reducing the gate's soft error rate (SER). Moreover, the decoupling cells facilitate the suppression of SET pulses propagating through the gate. It has been shown that the decoupling cells may be a competitive alternative to gate upsizing and gate duplication for hardening the gates with lower critical charge and multiple (3 or 4) inputs, as well as for filtering the short SET pulses induced by low-LET particles. New York IEEE 2019 4 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) 978-1-5386-9562-3 361 364 10.1109/ICECS.2018.8617996 Hasso-Plattner-Institut für Digital Engineering GmbH OPUS4-58446 Wissenschaftlicher Artikel Li, Yuanqing; Breitenreiter, Anselm; Andjelkovic, Marko; Chen, Junchao; Babic, Milan; Krstić, Miloš Double cell upsets mitigation through triple modular redundancy A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit. Oxford Elsevier 2020 8 Microelectronics Journal 96 10.1016/j.mejo.2019.104683 Institut für Informatik und Computational Science OPUS4-54074 misc Krstić, Miloš; Jentzsch, Anne-Kristin Reliability, safety and security of the electronics in automated driving vehicles - joint lab lecturing approach This paper proposes an education approach for master and bachelor students to enhance their skills in the area of reliability, safety and security of the electronic components in automated driving. The approach is based on the active synergetic work of research institutes, academia and industry in the frame of joint lab. As an example, the jointly organized summer school with the respective focus is organized and elaborated. New York IEEE 2018 2 2018 12TH European Workshop on Microelectronics Education (EWME) 978-1-5386-1157-9 21 22 Institut für Informatik und Computational Science