@book{SaposhnikovSaposhnikovMorozovetal.2004,
  author    = {Saposhnikov, V. V. and Saposhnikov, Vl. V. and Morozov, Alexei and G{\"o}ssel, Michael},
  title     = {Necessary and Sufficient Conditions for the Existence of Self-Checking Circuits ba Use of Complementary Circuits},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {2004, 1},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ.},
  address   = {Potsdam},
  issn      = {0946-7580},
  pages     = {11 S.},
  year      = {2004},
  language  = {en}
}
@phdthesis{Andjelkovic2021,
  author    = {Andjelkovic, Marko},
  title     = {A methodology for characterization, modeling and mitigation of single event transient effects in CMOS standard combinational cells},
  doi       = {10.25932/publishup-53484},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-534843},
  school      = {Universit{\"a}t Potsdam},
  pages     = {xxiv, 216},
  year      = {2021},
  abstract  = {With the downscaling of CMOS technologies, the radiation-induced Single Event Transient (SET) effects in combinational logic have become a critical reliability issue for modern integrated circuits (ICs) intended for operation under harsh radiation conditions. The SET pulses generated in combinational logic may propagate through the circuit and eventually result in soft errors. It has thus become an imperative to address the SET effects in the early phases of the radiation-hard IC design. In general, the soft error mitigation solutions should accommodate both static and dynamic measures to ensure the optimal utilization of available resources. An efficient soft-error-aware design should address synergistically three main aspects: (i) characterization and modeling of soft errors, (ii) multi-level soft error mitigation, and (iii) online soft error monitoring. Although significant results have been achieved, the effectiveness of SET characterization methods, accuracy of predictive SET models, and efficiency of SET mitigation measures are still critical issues. Therefore, this work addresses the following topics: (i) Characterization and modeling of SET effects in standard combinational cells, (ii) Static mitigation of SET effects in standard combinational cells, and (iii) Online particle detection, as a support for dynamic soft error mitigation. Since the standard digital libraries are widely used in the design of radiation-hard ICs, the characterization of SET effects in standard cells and the availability of accurate SET models for the Soft Error Rate (SER) evaluation are the main prerequisites for efficient radiation-hard design. This work introduces an approach for the SPICE-based standard cell characterization with the reduced number of simulations, improved SET models and optimized SET sensitivity database. It has been shown that the inherent similarities in the SET response of logic cells for different input levels can be utilized to reduce the number of required simulations. Based on characterization results, the fitting models for the SET sensitivity metrics (critical charge, generated SET pulse width and propagated SET pulse width) have been developed. The proposed models are based on the principle of superposition, and they express explicitly the dependence of the SET sensitivity of individual combinational cells on design, operating and irradiation parameters. In contrast to the state-of-the-art characterization methodologies which employ extensive look-up tables (LUTs) for storing the simulation results, this work proposes the use of LUTs for storing the fitting coefficients of the SET sensitivity models derived from the characterization results. In that way the amount of characterization data in the SET sensitivity database is reduced significantly. The initial step in enhancing the robustness of combinational logic is the application of gate-level mitigation techniques. As a result, significant improvement of the overall SER can be achieved with minimum area, delay and power overheads. For the SET mitigation in standard cells, it is essential to employ the techniques that do not require modifying the cell structure. This work introduces the use of decoupling cells for improving the robustness of standard combinational cells. By insertion of two decoupling cells at the output of a target cell, the critical charge of the cell's output node is increased and the attenuation of short SETs is enhanced. In comparison to the most common gate-level techniques (gate upsizing and gate duplication), the proposed approach provides better SET filtering. However, as there is no single gate-level mitigation technique with optimal performance, a combination of multiple techniques is required. This work introduces a comprehensive characterization of gate-level mitigation techniques aimed to quantify their impact on the SET robustness improvement, as well as introduced area, delay and power overhead per gate. By characterizing the gate-level mitigation techniques together with the standard cells, the required effort in subsequent SER analysis of a target design can be reduced. The characterization database of the hardened standard cells can be utilized as a guideline for selection of the most appropriate mitigation solution for a given design. As a support for dynamic soft error mitigation techniques, it is important to enable the online detection of energetic particles causing the soft errors. This allows activating the power-greedy fault-tolerant configurations based on N-modular redundancy only at the high radiation levels. To enable such a functionality, it is necessary to monitor both the particle flux and the variation of particle LET, as these two parameters contribute significantly to the system SER. In this work, a particle detection approach based on custom-sized pulse stretching inverters is proposed. Employing the pulse stretching inverters connected in parallel enables to measure the particle flux in terms of the number of detected SETs, while the particle LET variations can be estimated from the distribution of SET pulse widths. This approach requires a purely digital processing logic, in contrast to the standard detectors which require complex mixed-signal processing. Besides the possibility of LET monitoring, additional advantages of the proposed particle detector are low detection latency and power consumption, and immunity to error accumulation. The results achieved in this thesis can serve as a basis for establishment of an overall soft-error-aware database for a given digital library, and a comprehensive multi-level radiation-hard design flow that can be implemented with the standard IC design tools. The following step will be to evaluate the achieved results with the irradiation experiments.},
  language  = {en}
}
@article{SchrapeAndjelkovicBreitenreiteretal.2021,
  author    = {Schrape, Oliver and Andjelkovic, Marko and Breitenreiter, Anselm and Zeidler, Steffen and Balashov, Alexey and Krstić, Miloš},
  title     = {Design and evaluation of radiation-hardened standard cell flip-flops},
  series = {IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers},
  volume    = {68},
  journal   = {IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers},
  number    = {11},
  publisher = {Inst. of Electr. and Electronics Engineers},
  address   = {New York, NY},
  issn      = {1549-8328},
  doi       = {10.1109/TCSI.2021.3109080},
  pages     = {4796 -- 4809},
  year      = {2021},
  abstract  = {Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant.},
  language  = {en}
}
@article{BreitenreiterAndjelkovićSchrapeetal.2022,
  author    = {Breitenreiter, Anselm and Andjelković, Marko and Schrape, Oliver and Krstić, Miloš},
  title     = {Fast error propagation probability estimates by answer set programming and approximate model counting},
  series = {IEEE Access},
  volume    = {10},
  journal   = {IEEE Access},
  publisher = {Inst. of Electr. and Electronics Engineers},
  address   = {Piscataway},
  issn      = {2169-3536},
  doi       = {10.1109/ACCESS.2022.3174564},
  pages     = {51814 -- 51825},
  year      = {2022},
  abstract  = {We present a method employing Answer Set Programming in combination with Approximate Model Counting for fast and accurate calculation of error propagation probabilities in digital circuits. By an efficient problem encoding, we achieve an input data format similar to a Verilog netlist so that extensive preprocessing is avoided. By a tight interconnection of our application with the underlying solver, we avoid iterating over fault sites and reduce calls to the solver. Several circuits were analyzed with varying numbers of considered cycles and different degrees of approximation. Our experiments show, that the runtime can be reduced by approximation by a factor of 91, whereas the error compared to the exact result is below 1\%.},
  language  = {en}
}
@article{GoesselSogomonyan1996,
  author    = {G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {A parity-preserving multi-input signature analyzer and it application for concurrent checking and BIST},
  year      = {1996},
  language  = {en}
}
@article{LiChenNofaletal.2018,
  author    = {Li, Yuanqing and Chen, Li and Nofal, Issam and Chen, Mo and Wang, Haibin and Liu, Rui and Chen, Qingyu and Krstić, Miloš and Shi, Shuting and Guo, Gang and Baeg, Sang H. and Wen, Shi-Jie and Wong, Richard},
  title     = {Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree},
  series = {Microelectronics reliability},
  volume    = {87},
  journal   = {Microelectronics reliability},
  publisher = {Elsevier},
  address   = {Oxford},
  issn      = {0026-2714},
  doi       = {10.1016/j.microrel.2018.05.016},
  pages     = {24 -- 32},
  year      = {2018},
  abstract  = {The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.},
  language  = {en}
}
@article{MorosovSaposhnikovSaposhnikovetal.1997,
  author    = {Morosov, Andrej and Saposhnikov, Vl. V. and Saposhnikov, V. V. and G{\"o}ssel, Michael},
  title     = {Design of self dual fault-secure combinational circuits},
  year      = {1997},
  language  = {en}
}
@article{SaposhnikovSaposhnikovDimitrievetal.1998,
  author    = {Saposhnikov, Vl. V. and Saposhnikov, V. V. and Dimitriev, Alexej and G{\"o}ssel, Michael},
  title     = {Self-dual duplication for error detection},
  year      = {1998},
  language  = {en}
}
@article{SeuringGoessel1999,
  author    = {Seuring, Markus and G{\"o}ssel, Michael},
  title     = {A structural approach for space compaction for sequential circuits},
  year      = {1999},
  language  = {en}
}
@article{HartjeGoesselSogomonyan1997,
  author    = {Hartje, Hendrik and G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {Synthesis of code-disjoint combinational circuits},
  year      = {1997},
  language  = {en}
}
@phdthesis{Weidling2016,
  author    = {Weidling, Stefan},
  title     = {Neue Ans{\"a}tze zur Verbesserung der Fehlertoleranz gegen{\"u}ber transienten Fehlern in sequentiellen Schaltungen},
  school      = {Universit{\"a}t Potsdam},
  pages     = {XII, 181},
  year      = {2016},
  language  = {de}
}
@misc{KrstićJentzsch2018,
  author    = {Krstić, Miloš and Jentzsch, Anne-Kristin},
  title     = {Reliability, safety and security of the electronics in automated driving vehicles - joint lab lecturing approach},
  series = {2018 12TH European Workshop on Microelectronics Education (EWME)},
  journal   = {2018 12TH European Workshop on Microelectronics Education (EWME)},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-5386-1157-9},
  pages     = {21 -- 22},
  year      = {2018},
  abstract  = {This paper proposes an education approach for master and bachelor students to enhance their skills in the area of reliability, safety and security of the electronic components in automated driving. The approach is based on the active synergetic work of research institutes, academia and industry in the frame of joint lab. As an example, the jointly organized summer school with the respective focus is organized and elaborated.},
  language  = {en}
}
@article{SinghSogomonyanGoesseletal.1999,
  author    = {Singh, Adit D. and Sogomonyan, Egor S. and G{\"o}ssel, Michael and Seuring, Markus},
  title     = {Testability evaluation of sequential designs incorporating the multi-mode scannable memory element},
  year      = {1999},
  language  = {en}
}
@article{SaposhnikovSaposhnikovGoesseletal.1999,
  author    = {Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael and Morosov, Andrej},
  title     = {A method of construction of combinational self-checking units with detection of all single faults},
  year      = {1999},
  language  = {en}
}
@article{GoesselSogomonyan1994,
  author    = {G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {Self-parity combinational-circuits for self-testing, concurrent fault-detection and parity scan design},
  year      = {1994},
  language  = {en}
}
@article{GoesselSogomonyanMorosov1999,
  author    = {G{\"o}ssel, Michael and Sogomonyan, Egor S. and Morosov, Andrej},
  title     = {A new totally error propagating compactor for arbitrary cores with digital interfaces},
  year      = {1999},
  language  = {en}
}
@article{GoesselMorosovSaposhnikovetal.1994,
  author    = {G{\"o}ssel, Michael and Morosov, Andrej and Saposhnikov, V. V. and Saposhnikov, VL. V.},
  title     = {Design of combinational self-testing devices with unidirectionally independent outputs},
  year      = {1994},
  language  = {en}
}
@book{MarienfeldSogomonyanOcheretnijetal.2005,
  author    = {Marienfeld, Daniel and Sogomonyan, Egor S. and Ocheretnij, V. and G{\"o}ssel, Michael},
  title     = {Self-checking Output-duplicated Booth-2 Multiplier},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {2005, 1},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ.},
  address   = {Potsdam},
  issn      = {0946-7580},
  year      = {2005},
  language  = {en}
}
@article{SogomonyanSinghGoessel1998,
  author    = {Sogomonyan, Egor S. and Singh, Adit D. and G{\"o}ssel, Michael},
  title     = {A scan based concrrent BIST approach for low cost on-line testing},
  year      = {1998},
  language  = {en}
}
@book{SogomonyanMarienfeldGoessel2006,
  author    = {Sogomonyan, Egor S. and Marienfeld, Daniel and G{\"o}ssel, Michael},
  title     = {Fehlerkorrektur und Fehlererkennung},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {2006, 3},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ.},
  address   = {Potsdam},
  issn      = {0946-7580},
  pages     = {31, 8 S.},
  year      = {2006},
  language  = {de}
}
@phdthesis{Niess2016,
  author    = {Nieß, G{\"u}nther},
  title     = {Modellierung und Erkennung von technischen Fehlern mittels linearer und nichtlinearer Codes},
  school      = {Universit{\"a}t Potsdam},
  pages     = {V, 97},
  year      = {2016},
  language  = {de}
}
@book{BoernerGoessel2005,
  author    = {B{\"o}rner, Ferdinand and G{\"o}ssel, Michael},
  title     = {Grundlagen digitaler Systeme},
  publisher = {Univ.-Verl.},
  address   = {Potsdam},
  isbn      = {978-3-937786-46-9},
  pages     = {95 S.},
  year      = {2005},
  language  = {de}
}
@article{DmitrievSaposhnikovSaposhnikovetal.1999,
  author    = {Dmitriev, Alexej and Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael},
  title     = {Self-dual sequential circuits for concurrent chechking},
  isbn      = {0-7695-0390-X ; 0-7695-0391-8},
  year      = {1999},
  language  = {en}
}
@book{SogomonyanMarienfeldOcheretnijetal.2003,
  author    = {Sogomonyan, Egor S. and Marienfeld, Daniel and Ocheretnij, V. and G{\"o}ssel, Michael},
  title     = {A new self-checking sum-bit duplicated carry-select adder},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {2003, 5},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ.},
  address   = {Potsdam},
  issn      = {0946-7580},
  pages     = {10 S.},
  year      = {2003},
  language  = {en}
}
@article{SogomonyanSinghGoessel1999,
  author    = {Sogomonyan, Egor S. and Singh, Adit D. and G{\"o}ssel, Michael},
  title     = {A multi-mode scannable memory element for high test application efficiency and delay testing},
  year      = {1999},
  language  = {en}
}
@book{WuKarriKuznetsovetal.2003,
  author    = {Wu, K. and Karri, R. and Kuznetsov, Grigory and G{\"o}ssel, Michael},
  title     = {Low Cost Concurrent Error Detection for the Advanced Encryption Standart},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {2003, 8},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ.},
  address   = {Potsdam},
  issn      = {0946-7580},
  pages     = {10 S.},
  year      = {2003},
  language  = {en}
}
@book{BoernerGoessel2001,
  author    = {B{\"o}rner, Ferdinand and G{\"o}ssel, Michael},
  title     = {Grundlagen digitaler Systeme},
  editor    = {G{\"o}ssel, Michael},
  publisher = {Univ.-Bibliothek Publ.-Stelle},
  address   = {Potsdam},
  isbn      = {3-935024-34-7},
  pages     = {95 S. : graph. Darst.},
  year      = {2001},
  language  = {de}
}
@book{SapoznikovSapoznikovGoessel2001,
  author    = {Sapoznikov, V. V. and Sapoznikov, VL. V. and G{\"o}ssel, Michael},
  title     = {Samodvojstvennye diskretnye ustrojstva},
  publisher = {?nergoatomizdat},
  address   = {Sankt-Peterburg},
  isbn      = {5-283-04748-2},
  pages     = {330 S.},
  year      = {2001},
  language  = {ru}
}
@book{BoernerGoessel2000,
  author    = {B{\"o}rner, Ferdinand and G{\"o}ssel, Michael},
  title     = {Grundlagen digitaler Systeme},
  publisher = {Univ.-Bibliothek Publ.-Stelle},
  address   = {Potsdam},
  isbn      = {3-9806494-9-0},
  pages     = {61 S.},
  year      = {2000},
  language  = {de}
}
@article{OcheretnijGoesselSogomonyanetal.2006,
  author    = {Ocheretnij, Vitalij and G{\"o}ssel, Michael and Sogomonyan, Egor S. and Marienfeld, Daniel},
  title     = {Modulo p=3 checking for a carry select adder},
  doi       = {10.1007/s10836-006-6260-8},
  year      = {2006},
  abstract  = {In this paper a self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20\%. No restrictions are imposed on the design of the adder blocks},
  language  = {en}
}
@article{OtscheretnijSaposhnikovSaposhnikovetal.1999,
  author    = {Otscheretnij, Vitalij and Saposhnikov, Vl. V. and Saposhnikov, V. V. and G{\"o}ssel, Michael},
  title     = {Fault-tolerant self-dual circuits},
  year      = {1999},
  language  = {en}
}
@article{SaposhnikovMoshaninSaposhnikovetal.1999,
  author    = {Saposhnikov, Vl. V. V. V. and Moshanin, Vl. and Saposhnikov, V. V. and G{\"o}ssel, Michael},
  title     = {Experimental results for self-dual multi-output combinational circuits},
  year      = {1999},
  language  = {en}
}
@article{GoesselDimitrievSaposhnikovetal.1999,
  author    = {G{\"o}ssel, Michael and Dimitriev, Alexej and Saposhnikov, V. V. and Saposhnikov, Vl. V.},
  title     = {Eine selbsttestende Struktur zur on-line Fehlererkennung in kombinatorischen Schaltungen},
  year      = {1999},
  language  = {de}
}
@article{SaposhnikovOcheretnijSaposhnikovetal.1999,
  author    = {Saposhnikov, Vl. V. and Ocheretnij, V. and Saposhnikov, V. V. and G{\"o}ssel, Michael},
  title     = {Modified TMR-system with reduced hardware overhead},
  year      = {1999},
  language  = {en}
}
@article{GoesselSogomonyan1999,
  author    = {G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {New totally self-checking ripple and carry look-ahead adders},
  year      = {1999},
  language  = {en}
}
@article{Goessel1999,
  author    = {G{\"o}ssel, Michael},
  title     = {A new method of redundancy addition for circuit optimization},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {1999, 08},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ.},
  address   = {Potsdam},
  issn      = {0946-7580},
  pages     = {9 Bl.},
  year      = {1999},
  language  = {en}
}
@article{BogueJuergensenGoessel1994,
  author    = {Bogue, Ted and J{\"u}rgensen, Helmut and G{\"o}ssel, Michael},
  title     = {Design of cover circuits for monitoring the output of a MISR},
  isbn      = {0-8186-6307-3 , 0-8186-6306-5},
  year      = {1994},
  language  = {en}
}
@article{MorosovSaposhnikovSaposhnikovetal.1997,
  author    = {Morosov, Andrej and Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael},
  title     = {Ein Transformationsalgorithmus einer kombinatorischen Schaltung in eine monotone Schaltung},
  year      = {1997},
  language  = {de}
}
@article{SaposhnikovDimitrievGoesseletal.1996,
  author    = {Saposhnikov, Vl. V. and Dimitriev, Alexej and G{\"o}ssel, Michael and Saposhnikov, Va. V.},
  title     = {Self-dual parity checking - a new method for on-line testing},
  year      = {1996},
  language  = {en}
}
@article{GoesselSogomonyan1994,
  author    = {G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design},
  year      = {1994},
  language  = {en}
}
@article{KunduSogomonyanGoesseletal.1996,
  author    = {Kundu, S. and Sogomonyan, Egor S. and G{\"o}ssel, Michael and Tarnick, Steffen},
  title     = {Self-checking comparator with one periodiv output},
  year      = {1996},
  language  = {en}
}
@article{HartjeSogomonyanGoessel1997,
  author    = {Hartje, Hendrik and Sogomonyan, Egor S. and G{\"o}ssel, Michael},
  title     = {Code disjoint circuits for partity codes},
  year      = {1997},
  language  = {en}
}
@article{BogueJuergensenGoessel1995,
  author    = {Bogue, Ted and J{\"u}rgensen, Helmut and G{\"o}ssel, Michael},
  title     = {BIST with negligible aliasing through random cover circuits},
  year      = {1995},
  language  = {en}
}
@article{RabenaltRichterPoehletal.2012,
  author    = {Rabenalt, Thomas and Richter, Michael and P{\"o}hl, Frank and G{\"o}ssel, Michael},
  title     = {Highly efficient test response compaction using a hierarchical x-masking technique},
  series = {IEEE transactions on computer-aided design of integrated circuits and systems},
  volume    = {31},
  journal   = {IEEE transactions on computer-aided design of integrated circuits and systems},
  number    = {6},
  publisher = {Inst. of Electr. and Electronics Engineers},
  address   = {Piscataway},
  issn      = {0278-0070},
  doi       = {10.1109/TCAD.2011.2181847},
  pages     = {950 -- 957},
  year      = {2012},
  abstract  = {This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.},
  language  = {en}
}
@article{DugWeidlingSogomonyanetal.2020,
  author    = {Dug, Mehmed and Weidling, Stefan and Sogomonyan, Egor and Jokic, Dejan and Krstić, Miloš},
  title     = {Full error detection and correction method applied on pipelined structure using two approaches},
  series = {Journal of circuits, systems and computers},
  volume    = {29},
  journal   = {Journal of circuits, systems and computers},
  number    = {13},
  publisher = {World Scientific},
  address   = {Singapore},
  issn      = {0218-1266},
  doi       = {10.1142/S0218126620502187},
  pages     = {15},
  year      = {2020},
  abstract  = {In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.},
  language  = {en}
}
@article{LiBreitenreiterAndjelkovicetal.2020,
  author    = {Li, Yuanqing and Breitenreiter, Anselm and Andjelkovic, Marko and Chen, Junchao and Babic, Milan and Krstić, Miloš},
  title     = {Double cell upsets mitigation through triple modular redundancy},
  series = {Microelectronics Journal},
  volume    = {96},
  journal   = {Microelectronics Journal},
  publisher = {Elsevier},
  address   = {Oxford},
  issn      = {0026-2692},
  doi       = {10.1016/j.mejo.2019.104683},
  pages     = {8},
  year      = {2020},
  abstract  = {A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3\% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.},
  language  = {en}
}
@phdthesis{Hosp2015,
  author    = {Hosp, Sven},
  title     = {Modifizierte Cross-Party Codes zur schnellen Mehrbit-Fehlerkorrektur},
  pages     = {105},
  year      = {2015},
  language  = {de}
}
@article{AndjelkovicSimevskiChenetal.2022,
  author    = {Andjelkovic, Marko and Simevski, Aleksandar and Chen, Junchao and Schrape, Oliver and Stamenkovic, Zoran and Krstić, Miloš and Ilic, Stefan and Ristic, Goran and Jaksic, Aleksandar and Vasovic, Nikola and Duane, Russell and Palma, Alberto J. and Lallena, Antonio M. and Carvajal, Miguel A.},
  title     = {A design concept for radiation hardened RADFET readout system for space applications},
  series = {Microprocessors and microsystems},
  volume    = {90},
  journal   = {Microprocessors and microsystems},
  publisher = {Elsevier},
  address   = {Amsterdam},
  issn      = {0141-9331},
  doi       = {10.1016/j.micpro.2022.104486},
  pages     = {18},
  year      = {2022},
  abstract  = {Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET's response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions.},
  language  = {en}
}
@article{RisticIlicAndjelkovicetal.2022,
  author    = {Ristic, Goran S. and Ilic, Stefan D. and Andjelkovic, Marko S. and Duane, Russell and Palma, Alberto J. and Lalena, Antonio M. and Krstić, Miloš and Jaksic, Aleksandar B.},
  title     = {Sensitivity and fading of irradiated RADFETs with different gate voltages},
  series = {Nuclear Instruments and Methods in Physics Research Section A},
  volume    = {1029},
  journal   = {Nuclear Instruments and Methods in Physics Research Section A},
  publisher = {Elsevier},
  address   = {Amsterdam},
  issn      = {0168-9002},
  doi       = {10.1016/j.nima.2022.166473},
  pages     = {7},
  year      = {2022},
  abstract  = {The radiation-sensitive field-effect transistors (RADFETs) with an oxide thickness of 400 nm are irradiated with gate voltages of 2, 4 and 6 V, and without gate voltage. A detailed analysis of the mechanisms responsible for the creation of traps during irradiation is performed. The creation of the traps in the oxide, near and at the silicon/silicon-dioxide (Si/SiO2) interface during irradiation is modelled very well. This modelling can also be used for other MOS transistors containing SiO2. The behaviour of radiation traps during postirradiation annealing is analysed, and the corresponding functions for their modelling are obtained. The switching traps (STs) do not have significant influence on threshold voltage shift, and two radiation-induced trap types fit the fixed traps (FTs) very well. The fading does not depend on the positive gate voltage applied during irradiation, but it is twice lower in case there is no gate voltage. A new dosimetric parameter, called the Golden Ratio (GR), is proposed, which represents the ratio between the threshold voltage shift after irradiation and fading after spontaneous annealing. This parameter can be useful for comparing MOS dosimeters.},
  language  = {en}
}
@phdthesis{Duchrau2024,
  author    = {Duchrau, Georg},
  title     = {M{\"o}glichkeiten und Grenzen des erweiterten Cross Parity Codes},
  school      = {Universit{\"a}t Potsdam},
  pages     = {93},
  year      = {2024},
  language  = {de}
}
@phdthesis{Wang2011,
  author    = {Wang, Long},
  title     = {X-tracking the usage interest on web sites},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-51077},
  school      = {Universit{\"a}t Potsdam},
  year      = {2011},
  abstract  = {The exponential expanding of the numbers of web sites and Internet users makes WWW the most important global information resource. From information publishing and electronic commerce to entertainment and social networking, the Web allows an inexpensive and efficient access to the services provided by individuals and institutions. The basic units for distributing these services are the web sites scattered throughout the world. However, the extreme fragility of web services and content, the high competence between similar services supplied by different sites, and the wide geographic distributions of the web users drive the urgent requirement from the web managers to track and understand the usage interest of their web customers. This thesis, "X-tracking the Usage Interest on Web Sites", aims to fulfill this requirement. "X" stands two meanings: one is that the usage interest differs from various web sites, and the other is that usage interest is depicted from multi aspects: internal and external, structural and conceptual, objective and subjective. "Tracking" shows that our concentration is on locating and measuring the differences and changes among usage patterns. This thesis presents the methodologies on discovering usage interest on three kinds of web sites: the public information portal site, e-learning site that provides kinds of streaming lectures and social site that supplies the public discussions on IT issues. On different sites, we concentrate on different issues related with mining usage interest. The educational information portal sites were the first implementation scenarios on discovering usage patterns and optimizing the organization of web services. In such cases, the usage patterns are modeled as frequent page sets, navigation paths, navigation structures or graphs. However, a necessary requirement is to rebuild the individual behaviors from usage history. We give a systematic study on how to rebuild individual behaviors. Besides, this thesis shows a new strategy on building content clusters based on pair browsing retrieved from usage logs. The difference between such clusters and the original web structure displays the distance between the destinations from usage side and the expectations from design side. Moreover, we study the problem on tracking the changes of usage patterns in their life cycles. The changes are described from internal side integrating conceptual and structure features, and from external side for the physical features; and described from local side measuring the difference between two time spans, and global side showing the change tendency along the life cycle. A platform, Web-Cares, is developed to discover the usage interest, to measure the difference between usage interest and site expectation and to track the changes of usage patterns. E-learning site provides the teaching materials such as slides, recorded lecture videos and exercise sheets. We focus on discovering the learning interest on streaming lectures, such as real medias, mp4 and flash clips. Compared to the information portal site, the usage on streaming lectures encapsulates the variables such as viewing time and actions during learning processes. The learning interest is discovered in the form of answering 6 questions, which covers finding the relations between pieces of lectures and the preference among different forms of lectures. We prefer on detecting the changes of learning interest on the same course from different semesters. The differences on the content and structure between two courses leverage the changes on the learning interest. We give an algorithm on measuring the difference on learning interest integrated with similarity comparison between courses. A search engine, TASK-Moniminer, is created to help the teacher query the learning interest on their streaming lectures on tele-TASK site. Social site acts as an online community attracting web users to discuss the common topics and share their interesting information. Compared to the public information portal site and e-learning web site, the rich interactions among users and web content bring the wider range of content quality, on the other hand, provide more possibilities to express and model usage interest. We propose a framework on finding and recommending high reputation articles in a social site. We observed that the reputation is classified into global and local categories; the quality of the articles having high reputation is related with the content features. Based on these observations, our framework is implemented firstly by finding the articles having global or local reputation, and secondly clustering articles based on their content relations, and then the articles are selected and recommended from each cluster based on their reputation ranks.},
  language  = {en}
}
@phdthesis{Schrape2023,
  author    = {Schrape, Oliver},
  title     = {Methodology for standard cell-based design and implementation of reliable and robust hardware systems},
  doi       = {10.25932/publishup-58932},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-589326},
  school      = {Universit{\"a}t Potsdam},
  pages     = {xi, 181},
  year      = {2023},
  abstract  = {Reliable and robust data processing is one of the hardest requirements for systems in fields such as medicine, security, automotive, aviation, and space, to prevent critical system failures caused by changes in operating or environmental conditions. In particular, Signal Integrity (SI) effects such as crosstalk may distort the signal information in sensitive mixed-signal designs. A challenge for hardware systems used in the space are radiation effects. Namely, Single Event Effects (SEEs) induced by high-energy particle hits may lead to faulty computation, corrupted configuration settings, undesired system behavior, or even total malfunction. Since these applications require an extra effort in design and implementation, it is beneficial to master the standard cell design process and corresponding design flow methodologies optimized for such challenges. Especially for reliable, low-noise differential signaling logic such as Current Mode Logic (CML), a digital design flow is an orthogonal approach compared to traditional manual design. As a consequence, mandatory preliminary considerations need to be addressed in more detail. First of all, standard cell library concepts with suitable cell extensions for reliable systems and robust space applications have to be elaborated. Resulting design concepts at the cell level should enable the logical synthesis for differential logic design or improve the radiation-hardness. In parallel, the main objectives of the proposed cell architectures are to reduce the occupied area, power, and delay overhead. Second, a special setup for standard cell characterization is additionally required for a proper and accurate logic gate modeling. Last but not least, design methodologies for mandatory design flow stages such as logic synthesis and place and route need to be developed for the respective hardware systems to keep the reliability or the radiation-hardness at an acceptable level. This Thesis proposes and investigates standard cell-based design methodologies and techniques for reliable and robust hardware systems implemented in a conventional semi-conductor technology. The focus of this work is on reliable differential logic design and robust radiation-hardening-by-design circuits. The synergistic connections of the digital design flow stages are systematically addressed for these two types of hardware systems. In more detail, a library for differential logic is extended with single-ended pseudo-gates for intermediate design steps to support the logic synthesis and layout generation with commercial Computer-Aided Design (CAD) tools. Special cell layouts are proposed to relax signal routing. A library set for space applications is similarly extended by novel Radiation-Hardening-by-Design (RHBD) Triple Modular Redundancy (TMR) cells, enabling a one fault correction. Therein, additional optimized architectures for glitch filter cells, robust scannable and self-correcting flip-flops, and clock-gates are proposed. The circuit concepts and the physical layout representation views of the differential logic gates and the RHBD cells are discussed. However, the quality of results of designs depends implicitly on the accuracy of the standard cell characterization which is examined for both types therefore. The entire design flow is elaborated from the hardware design description to the layout representations. A 2-Phase routing approach together with an intermediate design conversion step is proposed after the initial place and route stage for reliable, pure differential designs, whereas a special constraining for RHBD applications in a standard technology is presented. The digital design flow for differential logic design is successfully demonstrated on a reliable differential bipolar CML application. A balanced routing result of its differential signal pairs is obtained by the proposed 2-Phase-routing approach. Moreover, the elaborated standard cell concepts and design methodology for RHBD circuits are applied to the digital part of a 7.5-15.5 MSPS 14-bit Analog-to-Digital Converter (ADC) and a complex microcontroller architecture. The ADC is implemented in an unhardened standard semiconductor technology and successfully verified by electrical measurements. The overhead of the proposed hardening approach is additionally evaluated by design exploration of the microcontroller application. Furthermore, the first obtained related measurement results of novel RHBD-∆TMR flip-flops show a radiation-tolerance up to a threshold Linear Energy Transfer (LET) of 46.1, 52.0, and 62.5 MeV cm2 mg-1 and savings in silicon area of 25-50 \% for selected TMR standard cell candidates. As a conclusion, the presented design concepts at the cell and library levels, as well as the design flow modifications are adaptable and transferable to other technology nodes. In particular, the design of hybrid solutions with integrated reliable differential logic modules together with robust radiation-tolerant circuit parts is enabled by the standard cell concepts and design methods proposed in this work.},
  language  = {en}
}
@article{HilscherBraunRichteretal.2009,
  author    = {Hilscher, Martin and Braun, Michael and Richter, Michael and Leininger, Andreas and G{\"o}ssel, Michael},
  title     = {X-tolerant test data compaction with accelerated shift registers},
  issn      = {0923-8174},
  doi       = {10.1007/s10836-009-5107-5},
  year      = {2009},
  abstract  = {Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution.},
  language  = {en}
}
@article{GoesselSogomonyan1996,
  author    = {G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {A new self-testing parity checker for ultra-reliable applications},
  year      = {1996},
  language  = {en}
}
@phdthesis{Seuring2000,
  author    = {Seuring, Markus},
  title     = {Output space compaction for testing and concurrent checking},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-0000165},
  school      = {Universit{\"a}t Potsdam},
  year      = {2000},
  abstract  = {In der Dissertation werden neue Entwurfsmethoden f{\"u}r Kompaktoren f{\"u}r die Ausg{\"a}nge von digitalen Schaltungen beschrieben, die die Anzahl der zu testenden Ausg{\"a}nge drastisch verkleinern und dabei die Testbarkeit der Schaltungen nur wenig oder gar nicht verschlechtern. Der erste Teil der Arbeit behandelt f{\"u}r kombinatorische Schaltungen Methoden, die die Struktur der Schaltungen beim Entwurf der Kompaktoren ber{\"u}cksichtigen. Verschiedene Algorithmen zur Analyse von Schaltungsstrukturen werden zum ersten Mal vorgestellt und untersucht. Die Komplexit{\"a}t der vorgestellten Verfahren zur Erzeugung von Kompaktoren ist linear bez{\"u}glich der Anzahl der Gatter in der Schaltung und ist damit auf sehr große Schaltungen anwendbar. Im zweiten Teil wird erstmals ein solches Verfahren f{\"u}r sequentielle Schaltkreise beschrieben. Dieses Verfahren baut im wesentlichen auf das erste auf. Der dritte Teil beschreibt eine Entwurfsmethode, die keine Informationen {\"u}ber die interne Struktur der Schaltung oder {\"u}ber das zugrundeliegende Fehlermodell ben{\"o}tigt. Der Entwurf basiert alleine auf einem vorgegebenen Satz von Testvektoren und die dazugeh{\"o}renden Testantworten der fehlerfreien Schaltung. Ein nach diesem Verfahren erzeugter Kompaktor maskiert keinen der Fehler, die durch das Testen mit den vorgegebenen Vektoren an den Ausg{\"a}ngen der Schaltung beobachtbar sind.},
  language  = {en}
}
@phdthesis{Chen2023,
  author    = {Chen, Junchao},
  title     = {A self-adaptive resilient method for implementing and managing the high-reliability processing system},
  doi       = {10.25932/publishup-58313},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-583139},
  school      = {Universit{\"a}t Potsdam},
  pages     = {XXIII, 167},
  year      = {2023},
  abstract  = {As a result of CMOS scaling, radiation-induced Single-Event Effects (SEEs) in electronic circuits became a critical reliability issue for modern Integrated Circuits (ICs) operating under harsh radiation conditions. SEEs can be triggered in combinational or sequential logic by the impact of high-energy particles, leading to destructive or non-destructive faults, resulting in data corruption or even system failure. Typically, the SEE mitigation methods are deployed statically in processing architectures based on the worst-case radiation conditions, which is most of the time unnecessary and results in a resource overhead. Moreover, the space radiation conditions are dynamically changing, especially during Solar Particle Events (SPEs). The intensity of space radiation can differ over five orders of magnitude within a few hours or days, resulting in several orders of magnitude fault probability variation in ICs during SPEs. This thesis introduces a comprehensive approach for designing a self-adaptive fault resilient multiprocessing system to overcome the static mitigation overhead issue. This work mainly addresses the following topics: (1) Design of on-chip radiation particle monitor for real-time radiation environment detection, (2) Investigation of space environment predictor, as support for solar particle events forecast, (3) Dynamic mode configuration in the resilient multiprocessing system. Therefore, according to detected and predicted in-flight space radiation conditions, the target system can be configured to use no mitigation or low-overhead mitigation during non-critical periods of time. The redundant resources can be used to improve system performance or save power. On the other hand, during increased radiation activity periods, such as SPEs, the mitigation methods can be dynamically configured appropriately depending on the real-time space radiation environment, resulting in higher system reliability. Thus, a dynamic trade-off in the target system between reliability, performance and power consumption in real-time can be achieved. All results of this work are evaluated in a highly reliable quad-core multiprocessing system that allows the self-adaptive setting of optimal radiation mitigation mechanisms during run-time. Proposed methods can serve as a basis for establishing a comprehensive self-adaptive resilient system design process. Successful implementation of the proposed design in the quad-core multiprocessor shows its application perspective also in the other designs.},
  language  = {en}
}
@phdthesis{Nordmann2020,
  author    = {Nordmann, Paul-Patrick},
  title     = {Fehlerkorrektur von Speicherfehlern mit Low-Density-Parity-Check-Codes},
  doi       = {10.25932/publishup-48048},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-480480},
  school      = {Universit{\"a}t Potsdam},
  pages     = {IV, 99, XII},
  year      = {2020},
  abstract  = {Die Fehlerkorrektur in der Codierungstheorie besch{\"a}ftigt sich mit der Erkennung und Behebung von Fehlern bei der {\"U}bertragung und auch Sicherung von Nachrichten. Hierbei wird die Nachricht durch zus{\"a}tzliche Informationen in ein Codewort kodiert. Diese Kodierungsverfahren besitzen verschiedene Anspr{\"u}che, wie zum Beispiel die maximale Anzahl der zu korrigierenden Fehler und die Geschwindigkeit der Korrektur. Ein g{\"a}ngiges Codierungsverfahren ist der BCH-Code, welches industriell f{\"u}r bis zu vier Fehler korrigiere Codes Verwendung findet. Ein Nachteil dieser Codes ist die technische Durchlaufzeit f{\"u}r die Berechnung der Fehlerstellen mit zunehmender Codel{\"a}nge. Die Dissertation stellt ein neues Codierungsverfahren vor, bei dem durch spezielle Anordnung kleinere Codel{\"a}ngen eines BCH-Codes ein langer Code erzeugt wird. Diese Anordnung geschieht {\"u}ber einen weiteren speziellen Code, einem LDPC-Code, welcher f{\"u}r eine schneller Fehlererkennung konzipiert ist. Hierf{\"u}r wird ein neues Konstruktionsverfahren vorgestellt, welches einen Code f{\"u}r einen beliebige L{\"a}nge mit vorgebbaren beliebigen Anzahl der zu korrigierenden Fehler vorgibt. Das vorgestellte Konstruktionsverfahren erzeugt zus{\"a}tzlich zum schnellen Verfahren der Fehlererkennung auch eine leicht und schnelle Ableitung eines Verfahrens zu Kodierung der Nachricht zum Codewort. Dies ist in der Literatur f{\"u}r die LDPC-Codes bis zum jetzigen Zeitpunkt einmalig. Durch die Konstruktion eines LDPC-Codes wird ein Verfahren vorgestellt wie dies mit einem BCH-Code kombiniert wird, wodurch eine Anordnung des BCH-Codes in Bl{\"o}cken erzeugt wird. Neben der allgemeinen Beschreibung dieses Codes, wird ein konkreter Code f{\"u}r eine 2-Bitfehlerkorrektur beschrieben. Diese besteht aus zwei Teilen, welche in verschiedene Varianten beschrieben und verglichen werden. F{\"u}r bestimmte L{\"a}ngen des BCH-Codes wird ein Problem bei der Korrektur aufgezeigt, welche einer algebraischen Regel folgt. Der BCH-Code wird sehr allgemein beschrieben, doch existiert durch bestimmte Voraussetzungen ein BCH-Code im engerem Sinne, welcher den Standard vorgibt. Dieser BCH-Code im engerem Sinne wird in dieser Dissertation modifiziert, so dass das algebraische Problem bei der 2-Bitfehler Korrektur bei der Kombination mit dem LDPC-Code nicht mehr existiert. Es wird gezeigt, dass nach der Modifikation der neue Code weiterhin ein BCH-Code im allgemeinen Sinne ist, welcher 2-Bitfehler korrigieren und 3-Bitfehler erkennen kann. Bei der technischen Umsetzung der Fehlerkorrektur wird des Weiteren gezeigt, dass die Durchlaufzeiten des modifizierten Codes im Vergleich zum BCH-Code schneller ist und weiteres Potential f{\"u}r Verbesserungen besitzt. Im letzten Kapitel wird gezeigt, dass sich dieser modifizierte Code mit beliebiger L{\"a}nge eignet f{\"u}r die Kombination mit dem LDPC-Code, wodurch dieses Verfahren nicht nur umf{\"a}nglicher in der L{\"a}nge zu nutzen ist, sondern auch durch die schnellere Dekodierung auch weitere Vorteile gegen{\"u}ber einem BCH-Code im engerem Sinne besitzt.},
  language  = {de}
}
@article{TavakoliAlirezazadehHedayatipouretal.2021,
  author    = {Tavakoli, Hamad and Alirezazadeh, Pendar and Hedayatipour, Ava and Nasib, A. H. Banijamali and Landwehr, Niels},
  title     = {Leaf image-based classification of some common bean cultivars using discriminative convolutional neural networks},
  series = {Computers and electronics in agriculture : COMPAG online ; an international journal},
  volume    = {181},
  journal   = {Computers and electronics in agriculture : COMPAG online ; an international journal},
  publisher = {Elsevier},
  address   = {Amsterdam [u.a.]},
  issn      = {0168-1699},
  doi       = {10.1016/j.compag.2020.105935},
  pages     = {11},
  year      = {2021},
  abstract  = {In recent years, many efforts have been made to apply image processing techniques for plant leaf identification. However, categorizing leaf images at the cultivar/variety level, because of the very low inter-class variability, is still a challenging task. In this research, we propose an automatic discriminative method based on convolutional neural networks (CNNs) for classifying 12 different cultivars of common beans that belong to three various species. We show that employing advanced loss functions, such as Additive Angular Margin Loss and Large Margin Cosine Loss, instead of the standard softmax loss function for the classification can yield better discrimination between classes and thereby mitigate the problem of low inter-class variability. The method was evaluated by classifying species (level I), cultivars from the same species (level II), and cultivars from different species (level III), based on images from the leaf foreside and backside. The results indicate that the performance of the classification algorithm on the leaf backside image dataset is superior. The maximum mean classification accuracies of 95.86, 91.37 and 86.87\% were obtained at the levels I, II and III, respectively. The proposed method outperforms the previous relevant works and provides a reliable approach for plant cultivars identification.},
  language  = {en}
}
@phdthesis{Morozov2005,
  author    = {Morozov, Alexei},
  title     = {Optimierung von Fehlererkennungsschaltungen auf der Grundlage von komplement{\"a}ren Erg{\"a}nzungen f{\"u}r 1-aus-3 und Berger Codes},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-5360},
  school      = {Universit{\"a}t Potsdam},
  year      = {2005},
  abstract  = {Die Dissertation stellt eine neue Herangehensweise an die L{\"o}sung der Aufgabe der funktionalen Diagnostik digitaler Systeme vor. In dieser Arbeit wird eine neue Methode f{\"u}r die Fehlererkennung vorgeschlagen, basierend auf der Logischen Erg{\"a}nzung und der Verwendung von Berger-Codes und dem 1-aus-3 Code. Die neue Fehlererkennungsmethode der Logischen Erg{\"a}nzung gestattet einen hohen Optimierungsgrad der ben{\"o}tigten Realisationsfl{\"a}che der konstruierten Fehlererkennungsschaltungen. Außerdem ist eins der wichtigen in dieser Dissertation gel{\"o}sten Probleme die Synthese vollst{\"a}ndig selbstpr{\"u}fender Schaltungen.},
  subject      = {logische Erg{\"a}nzung},
  language  = {de}
}
@article{GerberGoessel1994,
  author    = {Gerber, Stefan and G{\"o}ssel, Michael},
  title     = {Detection of permanent faults of a floating point adder by pseudoduplication},
  year      = {1994},
  language  = {en}
}
@article{BhattacharyaDimitrievGoessel2000,
  author    = {Bhattacharya, M. K. and Dimitriev, Alexej and G{\"o}ssel, Michael},
  title     = {Zero-aliasing space compresion using a single periodic output and its application to testing of embedded},
  year      = {2000},
  language  = {en}
}
@article{DimitrievSaposhnikovSaposhnikovetal.1999,
  author    = {Dimitriev, Alexej and Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael},
  title     = {Concurrent checking of sequential circuits by alternating inputs},
  year      = {1999},
  language  = {en}
}
@article{KuentzerKrstić2020,
  author    = {Kuentzer, Felipe A. and Krstić, Miloš},
  title     = {Soft error detection and correction architecture for asynchronous bundled data designs},
  series = {IEEE transactions on circuits and systems},
  volume    = {67},
  journal   = {IEEE transactions on circuits and systems},
  number    = {12},
  publisher = {Institute of Electrical and Electronics Engineers},
  address   = {New York},
  issn      = {1549-8328},
  doi       = {10.1109/TCSI.2020.2998911},
  pages     = {4883 -- 4894},
  year      = {2020},
  abstract  = {In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6\% to 17.6\%, and increasing energy efficiency, which can be up to 6.5\%.},
  language  = {en}
}
@article{SaposhnikovOtscheretnijSaposhnikovetal.1998,
  author    = {Saposhnikov, Vl. V. and Otscheretnij, Vitalij and Saposhnikov, V. V. and G{\"o}ssel, Michael},
  title     = {Design of Fault-Tolerant Circuits by self-dual Duplication},
  year      = {1998},
  language  = {en}
}
@article{MoschaninSaposhnikovSaposhnikovetal.1996,
  author    = {Moschanin, Wladimir and Saposhnikov, Vl. V. and Saposhnikov, Va. V. and G{\"o}ssel, Michael},
  title     = {Synthesis of self-dual multi-output combinational circuits for on-line Teting},
  year      = {1996},
  language  = {en}
}
@article{SeuringGoesselSogomonyan1998,
  author    = {Seuring, Markus and G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {Ein strukturelles Verfahren zur Kompaktierung von Schaltungsausgaben f{\"u}r online-Fehlererkennungen und Selbstests},
  year      = {1998},
  language  = {de}
}
@article{SogomonyanGoessel1996,
  author    = {Sogomonyan, Egor S. and G{\"o}ssel, Michael},
  title     = {Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems},
  year      = {1996},
  language  = {en}
}
@article{MorosovGoesselHartje1999,
  author    = {Morosov, Andrej and G{\"o}ssel, Michael and Hartje, Hendrik},
  title     = {Reduced area overhead of the input party for code-disjoint circuits},
  year      = {1999},
  language  = {en}
}
@article{SeuringGoessel1999,
  author    = {Seuring, Markus and G{\"o}ssel, Michael},
  title     = {A structural method for output compaction of sequential automata implemented as circuits},
  year      = {1999},
  language  = {en}
}
@book{SeuringGoessel1998,
  author    = {Seuring, Markus and G{\"o}ssel, Michael},
  title     = {A structural approach for space compaction for sequential circuits},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {1998, 05},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ.},
  address   = {Potsdam},
  issn      = {0946-7580},
  pages     = {16 Bl. : graph. Darst.},
  year      = {1998},
  language  = {en}
}
@article{HlawiczkaGoesselSogomonyan1997,
  author    = {Hlawiczka, A. and G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {A linear code-preserving signature analyzer COPMISR},
  isbn      = {0-8186-7810-0},
  year      = {1997},
  language  = {en}
}
@article{BogueGoesselJuergensenetal.1998,
  author    = {Bogue, Ted and G{\"o}ssel, Michael and J{\"u}rgensen, Helmut and Zorian, Yervant},
  title     = {Built-in self-Test with an alternating output},
  isbn      = {0-8186-8359-7},
  year      = {1998},
  language  = {en}
}
@article{OtscheretnijGoesselSaposhnikovetal.1998,
  author    = {Otscheretnij, Vitalij and G{\"o}ssel, Michael and Saposhnikov, Vl. V. and Saposhnikov, V. V.},
  title     = {Fault-tolerant self-dual circuits with error detection by parity- and group parity prediction},
  year      = {1998},
  language  = {en}
}
@article{SogomonyanSinghGoessel1998,
  author    = {Sogomonyan, Egor S. and Singh, Adit D. and G{\"o}ssel, Michael},
  title     = {A multi-mode scannable memory element for high test application efficiency and delay testing},
  year      = {1998},
  language  = {en}
}
@article{DimitrievSaposhnikovGoesseletal.1997,
  author    = {Dimitriev, Alexej and Saposhnikov, Vl. V. and G{\"o}ssel, Michael and Saposhnikov, V. V.},
  title     = {Self-dual duplication - a new method for on-line testing},
  year      = {1997},
  language  = {en}
}
@article{SaposhnikovMoshaninSaposhnikovetal.1997,
  author    = {Saposhnikov, Vl. V. and Moshanin, Vl. and Saposhnikov, V. V. and G{\"o}ssel, Michael},
  title     = {Self-dual multi output combinational circuits with output data compaction},
  year      = {1997},
  language  = {en}
}
@book{SeuringGoesselSogomonyan1997,
  author    = {Seuring, Markus and G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {A structural approach for space compaction for concurrent checking and BIST},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {1997, 01},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ. Potsdam},
  address   = {Potsdam [u.a.]},
  issn      = {0946-7580},
  pages     = {19 S. : Ill.},
  year      = {1997},
  language  = {en}
}
@article{GoesselSogomonyan1998,
  author    = {G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {On-line Test auf der Grundlage eines die Parit{\"a}t erhaltenden Signaturanalysators},
  year      = {1998},
  language  = {de}
}
@article{MorosovSaposhnikovGoessel1998,
  author    = {Morosov, Andrej and Saposhnikov, V. V. and G{\"o}ssel, Michael},
  title     = {Self-Checking circuits with unidiectionally independent outputs},
  year      = {1998},
  language  = {en}
}
@article{KrstićWeidlingPetrovicetal.,
  author    = {Krstić, Miloš and Weidling, Stefan and Petrovic, Vladimir and Sogomonyan, Egor S.},
  title     = {Enhanced architectures for soft error detection and correction in combinational and sequential circuits},
  series = {Microelectronics Reliability},
  volume    = {56},
  journal   = {Microelectronics Reliability},
  issn      = {0026-2714},
  pages     = {212 -- 220},
  abstract  = {In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master-slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26-28\% lower than the TMR.},
  language  = {en}
}
@phdthesis{Klockmann2022,
  author    = {Klockmann, Alexander},
  title     = {Modifizierte Unidirektionale Codes f{\"u}r Speicherfehler},
  pages     = {92},
  year      = {2022},
  abstract  = {Das Promotionsvorhaben verfolgt das Ziel, die Zuverl{\"a}ssigkeit der Datenspeicherung und die Speicherdichte von neu entwickelten Speichern (Emerging Memories) mit Multi-Level-Speicherzellen zu verbessern bzw. zu erh{\"o}hen. Hierf{\"u}r werden Codes zur Erkennung von unidirektionalen Fehlern analysiert, modifiziert und neu entwickelt, um sie innerhalb der neuen Speicher anwenden zu k{\"o}nnen. Der Fokus liegt dabei auf sog. Berger-Codes und m-aus-n-Codes. Da Multi-Level-Speicherzellen nicht mehr bin{\"a}r, sondern mit mehreren Leveln arbeiten, k{\"o}nnen bisher verwendete Codes nicht mehr verwendet werden, bzw. m{\"u}ssen entsprechend angepasst werden. Auf Basis der Berger-Codes und m-aus-n-Codes werden in dieser Arbeit neue Codes abgeleitet, welche in der Lage sind, Daten auch in mehrwertigen Systemen zu sch{\"u}tzen.},
  language  = {de}
}
@misc{Fandino2019,
  author    = {Fandi{\~n}o, Jorge},
  title     = {Founded (auto)epistemic equilibrium logic satisfies epistemic splitting},
  series = {Postprints der Universit{\"a}t Potsdam : Mathematisch-Naturwissenschaftliche Reihe},
  journal   = {Postprints der Universit{\"a}t Potsdam : Mathematisch-Naturwissenschaftliche Reihe},
  number    = {1060},
  issn      = {1866-8372},
  doi       = {10.25932/publishup-46968},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-469685},
  pages     = {671 -- 687},
  year      = {2019},
  abstract  = {In a recent line of research, two familiar concepts from logic programming semantics (unfounded sets and splitting) were extrapolated to the case of epistemic logic programs. The property of epistemic splitting provides a natural and modular way to understand programs without epistemic cycles but, surprisingly, was only fulfilled by Gelfond's original semantics (G91), among the many proposals in the literature. On the other hand, G91 may suffer from a kind of self-supported, unfounded derivations when epistemic cycles come into play. Recently, the absence of these derivations was also formalised as a property of epistemic semantics called foundedness. Moreover, a first semantics proved to satisfy foundedness was also proposed, the so-called Founded Autoepistemic Equilibrium Logic (FAEEL). In this paper, we prove that FAEEL also satisfies the epistemic splitting property something that, together with foundedness, was not fulfilled by any other approach up to date. To prove this result, we provide an alternative characterisation of FAEEL as a combination of G91 with a simpler logic we called Founded Epistemic Equilibrium Logic (FEEL), which is somehow an extrapolation of the stable model semantics to the modal logic S5.},
  language  = {en}
}
@article{CabalarFandinoFarinasdelCerro2021,
  author    = {Cabalar, Pedro and Fandi{\~n}o, Jorge and Fari{\~n}as del Cerro, Luis},
  title     = {Splitting epistemic logic programs},
  series = {Theory and practice of logic programming / publ. for the Association for Logic Programming},
  volume    = {21},
  journal   = {Theory and practice of logic programming / publ. for the Association for Logic Programming},
  number    = {3},
  publisher = {Cambridge Univ. Press},
  address   = {Cambridge [u.a.]},
  issn      = {1471-0684},
  doi       = {10.1017/S1471068420000058},
  pages     = {296 -- 316},
  year      = {2021},
  abstract  = {Epistemic logic programs constitute an extension of the stable model semantics to deal with new constructs called subjective literals. Informally speaking, a subjective literal allows checking whether some objective literal is true in all or some stable models. As it can be imagined, the associated semantics has proved to be non-trivial, since the truth of subjective literals may interfere with the set of stable models it is supposed to query. As a consequence, no clear agreement has been reached and different semantic proposals have been made in the literature. Unfortunately, comparison among these proposals has been limited to a study of their effect on individual examples, rather than identifying general properties to be checked. In this paper, we propose an extension of the well-known splitting property for logic programs to the epistemic case. We formally define when an arbitrary semantics satisfies the epistemic splitting property and examine some of the consequences that can be derived from that, including its relation to conformant planning and to epistemic constraints. Interestingly, we prove (through counterexamples) that most of the existing approaches fail to fulfill the epistemic splitting property, except the original semantics proposed by Gelfond 1991 and a recent proposal by the authors, called Founded Autoepistemic Equilibrium Logic.},
  language  = {en}
}
@misc{AguadoCabalarFandinoetal.2019,
  author    = {Aguado, Felicidad and Cabalar, Pedro and Fandi{\~n}o, Jorge and Pearce, David and Perez, Gilberto and Vidal, Concepcion},
  title     = {Revisiting explicit negation in answer set programming},
  series = {Postprints der Universit{\"a}t Potsdam : Mathematisch-Naturwissenschaftliche Reihe},
  journal   = {Postprints der Universit{\"a}t Potsdam : Mathematisch-Naturwissenschaftliche Reihe},
  number    = {1104},
  issn      = {1866-8372},
  doi       = {10.25932/publishup-46969},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-469697},
  pages     = {908 -- 924},
  year      = {2019},
  abstract  = {A common feature in Answer Set Programming is the use of a second negation, stronger than default negation and sometimes called explicit, strong or classical negation. This explicit negation is normally used in front of atoms, rather than allowing its use as a regular operator. In this paper we consider the arbitrary combination of explicit negation with nested expressions, as those defined by Lifschitz, Tang and Turner. We extend the concept of reduct for this new syntax and then prove that it can be captured by an extension of Equilibrium Logic with this second negation. We study some properties of this variant and compare to the already known combination of Equilibrium Logic with Nelson's strong negation.},
  language  = {en}
}
@phdthesis{Frank2024,
  author    = {Frank, Mario},
  title     = {On synthesising Linux kernel module components from Coq formalisations},
  doi       = {10.25932/publishup-64255},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-642558},
  school      = {Universit{\"a}t Potsdam},
  pages     = {IX, 78},
  year      = {2024},
  abstract  = {This thesis presents an attempt to use source code synthesised from Coq formalisations of device drivers for existing (micro)kernel operating systems, with a particular focus on the Linux Kernel. In the first part, the technical background and related work are described. The focus is here on the possible approaches to synthesising certified software with Coq, namely the extraction to functional languages using the Coq extraction plugin and the extraction to Clight code using the CertiCoq plugin. It is noted that the implementation of CertiCoq is verified, whereas this is not the case for the Coq extraction plugin. Consequently, there is a correctness guarantee for the generated Clight code which does not hold for the code being generated by the Coq extraction plugin. Furthermore, the differences between user space and kernel space software are discussed in relation to Linux device drivers. It is elaborated that it is not possible to generate working Linux kernel module components using the Coq extraction plugin without significant modifications. In contrast, it is possible to produce working user space drivers both with the Coq extraction plugin and CertiCoq. The subsequent parts describe the main contributions of the thesis. In the second part, it is demonstrated how to extend the Coq extraction plugin to synthesise foreign function calls between the functional language OCaml and the imperative language C. This approach has the potential to improve the type-safety of user space drivers. Furthermore, it is shown that the code being synthesised by CertiCoq cannot be used in kernel space without modifications to the necessary runtime. Consequently, the necessary modifications to the runtimes of CertiCoq and VeriFFI are introduced, resulting in the runtimes becoming compatible components of a Linux kernel module. Furthermore, justifications for the transformations are provided and possible further extensions to both plugins and solutions to failing garbage collection calls in kernel space are discussed. The third part presents a proof of concept device driver for the Linux Kernel. To achieve this, the event handler of the original PC Speaker driver is partially formalised in Coq. Furthermore, some relevant formal properties of the formalised functionality are discussed. Subsequently, a kernel module is defined, utilising the modified variants of CertiCoq and VeriFFI to compile a working device driver. It is furthermore shown that it is possible to compile the synthesised code with CompCert, thereby extending the guarantee of correctness to the assembly layer. This is followed by a performance evaluation that compares a naive formalisation of the PC speaker functionality with the original PC Speaker driver pointing out the weaknesses in the formalisation and possible improvements. The part closes with a summary of the results, their implications and open questions being raised. The last part lists all used sources, separated into scientific literature, documentations or reference manuals and artifacts, i.e. source code.},
  language  = {en}
}
@article{AguadoCabalarFandinoetal.2019,
  author    = {Aguado, Felicidad and Cabalar, Pedro and Fandi{\~n}o, Jorge and Pearce, David and Perez, Gilberto and Vidal, Concepcion},
  title     = {Forgetting auxiliary atoms in forks},
  series = {Artificial intelligence},
  volume    = {275},
  journal   = {Artificial intelligence},
  publisher = {Elsevier},
  address   = {Amsterdam},
  issn      = {0004-3702},
  doi       = {10.1016/j.artint.2019.07.005},
  pages     = {575 -- 601},
  year      = {2019},
  abstract  = {In this work we tackle the problem of checking strong equivalence of logic programs that may contain local auxiliary atoms, to be removed from their stable models and to be forbidden in any external context. We call this property projective strong equivalence (PSE). It has been recently proved that not any logic program containing auxiliary atoms can be reformulated, under PSE, as another logic program or formula without them - this is known as strongly persistent forgetting. In this paper, we introduce a conservative extension of Equilibrium Logic and its monotonic basis, the logic of Here-and-There, in which we deal with a new connective '|' we call fork. We provide a semantic characterisation of PSE for forks and use it to show that, in this extension, it is always possible to forget auxiliary atoms under strong persistence. We further define when the obtained fork is representable as a regular formula.},
  language  = {en}
}
@article{AguadoCabalarFandinoetal.2019,
  author    = {Aguado, Felicidad and Cabalar, Pedro and Fandi{\~n}o, Jorge and Pearce, David and Perez, Gilberto and Vidal-Peracho, Concepcion},
  title     = {Revisiting Explicit Negation in Answer Set Programming},
  series = {Theory and practice of logic programming},
  volume    = {19},
  journal   = {Theory and practice of logic programming},
  number    = {5-6},
  publisher = {Cambridge Univ. Press},
  address   = {New York},
  issn      = {1471-0684},
  doi       = {10.1017/S1471068419000267},
  pages     = {908 -- 924},
  year      = {2019},
  language  = {en}
}
@misc{Ziemann2024,
  type      = {Master Thesis},
  author    = {Ziemann, Felix},
  title     = {Entwicklung und Evaluation einer prototypischen Lernumgebung f{\"u}r das systematische Debugging logischer Fehler in Quellcode},
  doi       = {10.25932/publishup-63273},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-632734},
  school      = {Universit{\"a}t Potsdam},
  pages     = {x, 98},
  year      = {2024},
  abstract  = {Wo programmiert wird, da passieren Fehler. Um das Debugging, also die Suche sowie die Behebung von Fehlern in Quellcode, st{\"a}rker explizit zu adressieren, verfolgt die vorliegende Arbeit das Ziel, entlang einer prototypischen Lernumgebung sowohl ein systematisches Vorgehen w{\"a}hrend des Debuggings zu vermitteln als auch Gestaltungsfolgerungen f{\"u}r ebensolche Lernumgebungen zu identifizieren. Dazu wird die folgende Forschungsfrage gestellt: Wie verhalten sich die Lernenden w{\"a}hrend des kurzzeitigen Gebrauchs einer Lernumgebung nach dem Cognitive Apprenticeship-Ansatz mit dem Ziel der expliziten Vermittlung eines systematischen Debuggingvorgehens und welche Eindr{\"u}cke entstehen w{\"a}hrend der Bearbeitung? Zur Beantwortung dieser Forschungsfrage wurde orientierend an literaturbasierten Implikationen f{\"u}r die Vermittlung von Debugging und (medien-)didaktischen Gestaltungsaspekten eine prototypische Lernumgebung entwickelt und im Rahmen einer qualitativen Nutzerstudie mit Bachelorstudierenden informatischer Studieng{\"a}nge erprobt. Hierbei wurden zum einen anwendungsbezogene Verbesserungspotenziale identifiziert. Zum anderen zeigte sich insbesondere gegen{\"u}ber der Systematisierung des Debuggingprozesses innerhalb der Aufgabenbearbeitung eine positive Resonanz. Eine Untersuchung, inwieweit sich die Nutzung der Lernumgebung l{\"a}ngerfristig auf das Verhalten von Personen und ihre Vorgehensweisen w{\"a}hrend des Debuggings auswirkt, k{\"o}nnte Gegenstand kommender Arbeiten sein.},
  language  = {de}
}
@article{SchickBojahrHerzogetal.2014,
  author    = {Schick, Daniel and Bojahr, Andre and Herzog, Marc and Shayduk, Roman and von Korff Schmising, Clemens and Bargheer, Matias},
  title     = {Udkm1Dsim-A simulation toolkit for 1D ultrafast dynamics in condensed matter},
  series = {Computer physics communications : an international journal devoted to computational physics and computer programs in physics},
  volume    = {185},
  journal   = {Computer physics communications : an international journal devoted to computational physics and computer programs in physics},
  number    = {2},
  publisher = {Elsevier},
  address   = {Amsterdam},
  issn      = {0010-4655},
  doi       = {10.1016/j.cpc.2013.10.009},
  pages     = {651 -- 660},
  year      = {2014},
  abstract  = {The UDKM1DSIM toolbox is a collection of MATLAB (MathWorks Inc.) classes and routines to simulate the structural dynamics and the according X-ray diffraction response in one-dimensional crystalline sample structures upon an arbitrary time-dependent external stimulus, e.g. an ultrashort laser pulse. The toolbox provides the capabilities to define arbitrary layered structures on the atomic level including a rich database of corresponding element-specific physical properties. The excitation of ultrafast dynamics is represented by an N-temperature model which is commonly applied for ultrafast optical excitations. Structural dynamics due to thermal stress are calculated by a linear-chain model of masses and springs. The resulting X-ray diffraction response is computed by dynamical X-ray theory. The UDKM1DSIM toolbox is highly modular and allows for introducing user-defined results at any step in the simulation procedure. Program summary Program title: udkm1Dsim Catalogue identifier: AERH_v1_0 Program summary URL: http://cpc.cs.qub.ac.uk/summaries/AERH_v1_0.html Licensing provisions: BSD No. of lines in distributed program, including test data, etc.: 130221 No. of bytes in distributed program, including test data, etc.: 2746036 Distribution format: tar.gz Programming language: Matlab (MathWorks Inc.). Computer: PC/Workstation. Operating system: Running Matlab installation required (tested on MS Win XP -7, Ubuntu Linux 11.04-13.04). Has the code been vectorized or parallelized?: Parallelization for dynamical XRD computations. Number of processors used: 1-12 for Matlab Parallel Computing Toolbox; 1 - infinity for Matlab Distributed Computing Toolbox External routines: Optional: Matlab Parallel Computing Toolbox, Matlab Distributed Computing Toolbox Required (included in the package): mtimesx Fast Matrix Multiply for Matlab by James Tursa, xml io tools by Jaroslaw Tuszynski, textprogressbar by Paul Proteus Nature of problem: Simulate the lattice dynamics of 1D crystalline sample structures due to an ultrafast excitation including thermal transport and compute the corresponding transient X-ray diffraction pattern. Solution method: Restrictions: The program is restricted to 1D sample structures and is further limited to longitudinal acoustic phonon modes and symmetrical X-ray diffraction geometries. Unusual features: The program is highly modular and allows the inclusion of user-defined inputs at any time of the simulation procedure. Running time: The running time is highly dependent on the number of unit cells in the sample structure and other simulation parameters such as time span or angular grid for X-ray diffraction computations. However, the example files are computed in approx. 1-5 min each on a 8 Core Processor with 16 GB RAM available.},
  language  = {en}
}
@phdthesis{Hecher2021,
  author    = {Hecher, Markus},
  title     = {Advanced tools and methods for treewidth-based problem solving},
  doi       = {10.25932/publishup-51251},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-512519},
  school      = {Universit{\"a}t Potsdam},
  pages     = {xv, 184},
  year      = {2021},
  abstract  = {In the last decades, there was a notable progress in solving the well-known Boolean satisfiability (Sat) problem, which can be witnessed by powerful Sat solvers. One of the reasons why these solvers are so fast are structural properties of instances that are utilized by the solver's interna. This thesis deals with the well-studied structural property treewidth, which measures the closeness of an instance to being a tree. In fact, there are many problems parameterized by treewidth that are solvable in polynomial time in the instance size when parameterized by treewidth. In this work, we study advanced treewidth-based methods and tools for problems in knowledge representation and reasoning (KR). Thereby, we provide means to establish precise runtime results (upper bounds) for canonical problems relevant to KR. Then, we present a new type of problem reduction, which we call decomposition-guided (DG) that allows us to precisely monitor the treewidth when reducing from one problem to another problem. This new reduction type will be the basis for a long-open lower bound result for quantified Boolean formulas and allows us to design a new methodology for establishing runtime lower bounds for problems parameterized by treewidth. Finally, despite these lower bounds, we provide an efficient implementation of algorithms that adhere to treewidth. Our approach finds suitable abstractions of instances, which are subsequently refined in a recursive fashion, and it uses Sat solvers for solving subproblems. It turns out that our resulting solver is quite competitive for two canonical counting problems related to Sat.},
  language  = {en}
}
@misc{CabalarFandinoSchaubetal.2019,
  author    = {Cabalar, Pedro and Fandi{\~n}o, Jorge and Schaub, Torsten and Schellhorn, Sebastian},
  title     = {Lower Bound Founded Logic of Here-and-There},
  series = {Logics in Artificial Intelligence},
  volume    = {11468},
  journal   = {Logics in Artificial Intelligence},
  publisher = {Springer},
  address   = {Cham},
  isbn      = {978-3-030-19570-0},
  issn      = {0302-9743},
  doi       = {10.1007/978-3-030-19570-0_34},
  pages     = {509 -- 525},
  year      = {2019},
  abstract  = {A distinguishing feature of Answer Set Programming is that all atoms belonging to a stable model must be founded. That is, an atom must not only be true but provably true. This can be made precise by means of the constructive logic of Here-and-There, whose equilibrium models correspond to stable models. One way of looking at foundedness is to regard Boolean truth values as ordered by letting true be greater than false. Then, each Boolean variable takes the smallest truth value that can be proven for it. This idea was generalized by Aziz to ordered domains and applied to constraint satisfaction problems. As before, the idea is that a, say integer, variable gets only assigned to the smallest integer that can be justified. In this paper, we present a logical reconstruction of Aziz' idea in the setting of the logic of Here-and-There. More precisely, we start by defining the logic of Here-and-There with lower bound founded variables along with its equilibrium models and elaborate upon its formal properties. Finally, we compare our approach with related ones and sketch future work.},
  language  = {en}
}
@phdthesis{Thiele2011,
  author    = {Thiele, Sven},
  title     = {Modeling biological systems with Answer Set Programming},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-59383},
  school      = {Universit{\"a}t Potsdam},
  year      = {2011},
  abstract  = {Biology has made great progress in identifying and measuring the building blocks of life. The availability of high-throughput methods in molecular biology has dramatically accelerated the growth of biological knowledge for various organisms. The advancements in genomic, proteomic and metabolomic technologies allow for constructing complex models of biological systems. An increasing number of biological repositories is available on the web, incorporating thousands of biochemical reactions and genetic regulations. Systems Biology is a recent research trend in life science, which fosters a systemic view on biology. In Systems Biology one is interested in integrating the knowledge from all these different sources into models that capture the interaction of these entities. By studying these models one wants to understand the emerging properties of the whole system, such as robustness. However, both measurements as well as biological networks are prone to considerable incompleteness, heterogeneity and mutual inconsistency, which makes it highly non-trivial to draw biologically meaningful conclusions in an automated way. Therefore, we want to promote Answer Set Programming (ASP) as a tool for discrete modeling in Systems Biology. ASP is a declarative problem solving paradigm, in which a problem is encoded as a logic program such that its answer sets represent solutions to the problem. ASP has intrinsic features to cope with incompleteness, offers a rich modeling language and highly efficient solving technology. We present ASP solutions, for the analysis of genetic regulatory networks, determining consistency with observed measurements and identifying minimal causes for inconsistency. We extend this approach for computing minimal repairs on model and data that restore consistency. This method allows for predicting unobserved data even in case of inconsistency. Further, we present an ASP approach to metabolic network expansion. This approach exploits the easy characterization of reachability in ASP and its various reasoning methods, to explore the biosynthetic capabilities of metabolic reaction networks and generate hypotheses for extending the network. Finally, we present the BioASP library, a Python library which encapsulates our ASP solutions into the imperative programming paradigm. The library allows for an easy integration of ASP solution into system rich environments, as they exist in Systems Biology.},
  language  = {en}
}
@inproceedings{GebserHinrichsSchaubetal.2010,
  author    = {Gebser, Martin and Hinrichs, Henrik and Schaub, Torsten and Thiele, Sven},
  title     = {xpanda: a (simple) preprocessor for adding multi-valued propositions to ASP},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-41466},
  year      = {2010},
  abstract  = {We introduce a simple approach extending the input language of Answer Set Programming (ASP) systems by multi-valued propositions. Our approach is implemented as a (prototypical) preprocessor translating logic programs with multi-valued propositions into logic programs with Boolean propositions only. Our translation is modular and heavily benefits from the expressive input language of ASP. The resulting approach, along with its implementation, allows for solving interesting constraint satisfaction problems in ASP, showing a good performance.},
  language  = {en}
}
@article{CabalarDieguezSchaubetal.2020,
  author    = {Cabalar, Pedro and Dieguez, Martin and Schaub, Torsten and Schuhmann, Anna},
  title     = {Towards metric temporal answer set programming},
  series = {Theory and practice of logic programming},
  volume    = {20},
  journal   = {Theory and practice of logic programming},
  number    = {5},
  publisher = {Cambridge Univ. Press},
  address   = {Cambridge [u.a.]},
  issn      = {1471-0684},
  doi       = {10.1017/S1471068420000307},
  pages     = {783 -- 798},
  year      = {2020},
  abstract  = {We elaborate upon the theoretical foundations of a metric temporal extension of Answer Set Programming. In analogy to previous extensions of ASP with constructs from Linear Temporal and Dynamic Logic, we accomplish this in the setting of the logic of Here-and-There and its non-monotonic extension, called Equilibrium Logic. More precisely, we develop our logic on the same semantic underpinnings as its predecessors and thus use a simple time domain of bounded time steps. This allows us to compare all variants in a uniform framework and ultimately combine them in a common implementation.},
  language  = {en}
}
@article{PearceSarsakovSchaubetal.2002,
  author    = {Pearce, David and Sarsakov, Vladimir and Schaub, Torsten and Tompits, Hans and Woltran, Stefan},
  title     = {A polynomial translation of logic programs with nested expressions into disjunctive logic programs},
  isbn      = {3-540-43930-7},
  year      = {2002},
  language  = {en}
}
@article{AngerGebserJanhunenetal.2006,
  author    = {Anger, Christian and Gebser, Martin and Janhunen, Tomi and Schaub, Torsten},
  title     = {What's a head without a body?},
  year      = {2006},
  language  = {en}
}
@article{MileoSchaub2007,
  author    = {Mileo, Alessandra and Schaub, Torsten},
  title     = {Qualitative constraint enforcement in advanced policy specification},
  year      = {2007},
  language  = {en}
}
@phdthesis{Floeter2005,
  author    = {Fl{\"o}ter, Andr{\´e}},
  title     = {Analyzing biological expression data based on decision tree induction},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-6416},
  school      = {Universit{\"a}t Potsdam},
  year      = {2005},
  abstract  = {Modern biological analysis techniques supply scientists with various forms of data. One category of such data are the so called "expression data". These data indicate the quantities of biochemical compounds present in tissue samples. Recently, expression data can be generated at a high speed. This leads in turn to amounts of data no longer analysable by classical statistical techniques. Systems biology is the new field that focuses on the modelling of this information. At present, various methods are used for this purpose. One superordinate class of these meth­ods is machine learning. Methods of this kind had, until recently, predominantly been used for classification and prediction tasks. This neglected a powerful secondary benefit: the ability to induce interpretable models. Obtaining such models from data has become a key issue within Systems biology. Numerous approaches have been proposed and intensively discussed. This thesis focuses on the examination and exploitation of one basic technique: decision trees. The concept of comparing sets of decision trees is developed. This method offers the pos­sibility of identifying significant thresholds in continuous or discrete valued attributes through their corresponding set of decision trees. Finding significant thresholds in attributes is a means of identifying states in living organisms. Knowing about states is an invaluable clue to the un­derstanding of dynamic processes in organisms. Applied to metabolite concentration data, the proposed method was able to identify states which were not found with conventional techniques for threshold extraction. A second approach exploits the structure of sets of decision trees for the discovery of com­binatorial dependencies between attributes. Previous work on this issue has focused either on expensive computational methods or the interpretation of single decision trees ­ a very limited exploitation of the data. This has led to incomplete or unstable results. That is why a new method is developed that uses sets of decision trees to overcome these limitations. Both the introduced methods are available as software tools. They can be applied consecu­tively or separately. That way they make up a package of analytical tools that usefully supplement existing methods. By means of these tools, the newly introduced methods were able to confirm existing knowl­edge and to suggest interesting and new relationships between metabolites.},
  subject      = {Molekulare Bioinformatik},
  language  = {en}
}
@phdthesis{Gebser2011,
  author    = {Gebser, Martin},
  title     = {Proof theory and algorithms for answer set programming},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-55425},
  school      = {Universit{\"a}t Potsdam},
  year      = {2011},
  abstract  = {Answer Set Programming (ASP) is an emerging paradigm for declarative programming, in which a computational problem is specified by a logic program such that particular models, called answer sets, match solutions. ASP faces a growing range of applications, demanding for high-performance tools able to solve complex problems. ASP integrates ideas from a variety of neighboring fields. In particular, automated techniques to search for answer sets are inspired by Boolean Satisfiability (SAT) solving approaches. While the latter have firm proof-theoretic foundations, ASP lacks formal frameworks for characterizing and comparing solving methods. Furthermore, sophisticated search patterns of modern SAT solvers, successfully applied in areas like, e.g., model checking and verification, are not yet established in ASP solving. We address these deficiencies by, for one, providing proof-theoretic frameworks that allow for characterizing, comparing, and analyzing approaches to answer set computation. For another, we devise modern ASP solving algorithms that integrate and extend state-of-the-art techniques for Boolean constraint solving. We thus contribute to the understanding of existing ASP solving approaches and their interconnections as well as to their enhancement by incorporating sophisticated search patterns. The central idea of our approach is to identify atomic as well as composite constituents of a propositional logic program with Boolean variables. This enables us to describe fundamental inference steps, and to selectively combine them in proof-theoretic characterizations of various ASP solving methods. In particular, we show that different concepts of case analyses applied by existing ASP solvers implicate mutual exponential separations regarding their best-case complexities. We also develop a generic proof-theoretic framework amenable to language extensions, and we point out that exponential separations can likewise be obtained due to case analyses on them. We further exploit fundamental inference steps to derive Boolean constraints characterizing answer sets. They enable the conception of ASP solving algorithms including search patterns of modern SAT solvers, while also allowing for direct technology transfers between the areas of ASP and SAT solving. Beyond the search for one answer set of a logic program, we address the enumeration of answer sets and their projections to a subvocabulary, respectively. The algorithms we develop enable repetition-free enumeration in polynomial space without being intrusive, i.e., they do not necessitate any modifications of computations before an answer set is found. Our approach to ASP solving is implemented in clasp, a state-of-the-art Boolean constraint solver that has successfully participated in recent solver competitions. Although we do here not address the implementation techniques of clasp or all of its features, we present the principles of its success in the context of ASP solving.},
  language  = {en}
}
@article{DurzinskyMarwanOstrowskietal.2011,
  author    = {Durzinsky, Markus and Marwan, Wolfgang and Ostrowski, Max and Schaub, Torsten and Wagler, Annegret},
  title     = {Automatic network reconstruction using ASP},
  series = {Theory and practice of logic programming},
  volume    = {11},
  journal   = {Theory and practice of logic programming},
  publisher = {Cambridge Univ. Press},
  address   = {New York},
  issn      = {1471-0684},
  doi       = {10.1017/S1471068411000287},
  pages     = {749 -- 766},
  year      = {2011},
  abstract  = {Building biological models by inferring functional dependencies from experimental data is an important issue in Molecular Biology. To relieve the biologist from this traditionally manual process, various approaches have been proposed to increase the degree of automation. However, available approaches often yield a single model only, rely on specific assumptions, and/or use dedicated, heuristic algorithms that are intolerant to changing circumstances or requirements in the view of the rapid progress made in Biotechnology. Our aim is to provide a declarative solution to the problem by appeal to Answer Set Programming (ASP) overcoming these difficulties. We build upon an existing approach to Automatic Network Reconstruction proposed by part of the authors. This approach has firm mathematical foundations and is well suited for ASP due to its combinatorial flavor providing a characterization of all models explaining a set of experiments. The usage of ASP has several benefits over the existing heuristic algorithms. First, it is declarative and thus transparent for biological experts. Second, it is elaboration tolerant and thus allows for an easy exploration and incorporation of biological constraints. Third, it allows for exploring the entire space of possible models. Finally, our approach offers an excellent performance, matching existing, special-purpose systems.},
  language  = {en}
}