@inproceedings{KeilKonertDamniketal.2018, author = {Keil, Reinhard and Konert, Johannes and Damnik, Gregor and Gierl, Mark J. and Proske, Antje and K{\"o}rndle, Hermann and Narciss, Susanne and Wahl, Marina and H{\"o}lscher, Michael and Mariani, Ennio and Jaisli, Isabel and Tscherejkina, Anna and Morgiel, Anna and Moebert, Tobias and Herbstreit, Stephanie and M{\"a}ker, Daniela and Szalai, Cynthia and Braun, Iris and Kapp, Felix and Hara, Tenshi C. and Kubica, Tommy and Stumpf, Sarah}, title = {E-Learning Symposium 2018}, editor = {Lucke, Ulrike and Strickroth, Sven}, publisher = {Universit{\"a}tsverlag Potsdam}, address = {Potsdam}, doi = {10.25932/publishup-42071}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-420711}, pages = {71}, year = {2018}, abstract = {In den vergangenen Jahren sind viele E-Learning-Innovationen entstanden. Einige davon wurden auf den vergangenen E-Learning Symposien der Universit{\"a}t Potsdam pr{\"a}sentiert: Das erste E-Learning Symposium im Jahr 2012 konzentrierte sich auf unterschiedliche M{\"o}glichkeiten der Studierendenaktivierung und Lehrgestaltung. Das Symposium 2014 r{\"u}ckte vor allem die Studierenden ins Zentrum der Aufmerksamkeit. Im Jahr 2016 kam es durch das Zusammengehen des Symposiums mit der DeLFI-Tagung zu einer Fokussierung auf technische Innovationen. Doch was ist aus den Leuchtt{\"u}rmen von gestern geworden, und brauchen wir {\"u}berhaupt noch neue Leuchtt{\"u}rme? Das Symposium setzt sich in diesem Jahr unter dem Motto „Innovation und Nachhaltigkeit - (k)ein Gegensatz?" mit mediengest{\"u}tzten Lehr- und Lernprozessen im universit{\"a}ren Kontext auseinander und reflektiert aktuelle technische sowie didaktische Entwicklungen mit Blick auf deren mittel- bis langfristigen Einsatz in der Praxis. Dieser Tagungsband zum E-Learning Symposium 2018 an der Universit{\"a}t Potsdam beinhaltet eine Mischung von Forschungs- und Praxisbeitr{\"a}gen aus verschiedenen Fachdisziplinen und er{\"o}ffnet vielschichtige Perspektiven auf das Thema E-Learning. Dabei werden die Vielfalt der didaktischen Einsatzszenarien als auch die Potentiale von Werk-zeugen und Methoden der Informatik in ihrem Zusammenspiel beleuchtet. In seiner Keynote widmet sich Reinhard Keil dem Motto des Symposiums und geht der Nachhaltigkeit bei E-Learning-Projekten auf den Grund. Dabei analysiert und beleuchtet er anhand seiner {\"u}ber 15-j{\"a}hrigen Forschungspraxis die wichtigsten Wirkfaktoren und formuliert Empfehlungen zur Konzeption von E-Learning-Projekten. Im Gegensatz zu rein auf Kostenersparnis ausgerichteten (hochschul-)politischen Forderungen proklamiert er den Ansatz der hypothesengeleiteten Technikgestaltung, in der Nachhaltigkeit als Leitfrage oder Forschungsstrategie verstanden werden kann. In eine {\"a}hnliche Richtung geht der Beitrag von Iris Braun et al., die {\"u}ber Erfolgsfaktoren beim Einsatz von Audience Response Systemen in der universit{\"a}ren Lehre berichten. Ein weiteres aktuelles Thema, sowohl f{\"u}r die Bildungstechnologie als auch in den Bildungswissenschaften allgemein, ist die Kompetenzorientierung und -modellierung. Hier geht es darum (Probleml{\"o}se-)F{\"a}higkeiten gezielt zu beschreiben und in den Mittelpunkt der Lehre zu stellen. Johannes Konert stellt in einem eingeladenen Vortrag zwei Projekte vor, die den Prozess beginnend bei der Definition von Kompetenzen, deren Modellierung in einem semantischen maschinenlesbaren Format bis hin zur Erarbeitung von Methoden zur Kompetenzmessung und der elektronischen Zertifizierung aufzeigen. Dabei geht er auf technische M{\"o}glichkeiten, aber auch Grenzen ein. Auf einer spezifischeren Ebene besch{\"a}ftigt sich Sarah Stumpf mit digitalen bzw. mediendidaktischen Kompetenzen im Lehramtsstudium und stellt ein Framework f{\"u}r die F{\"o}rderung ebensolcher Kompetenzen bei angehenden Lehrkr{\"a}ften vor. Der Einsatz von E-Learning birgt noch einige Herausforderungen. Dabei geht es oft um die Verbindung von Didaktik und Technik, den Erhalt von Aufmerksamkeit oder den Aufwand f{\"u}r das Erstellen von interaktiven Lehr- und Lerninhalten. Drei Beitr{\"a}ge in diesem Tagungsband besch{\"a}ftigen sich mit dieser Thematik in unterschiedlichen Kontexten und zeigen Best-Practices und L{\"o}sungsans{\"a}tze auf: Der Beitrag von Martina Wahl und Michael H{\"o}lscher behandelt den besonderen Kontext von Blended Learning-Szenarien in berufsbegleitenden Studieng{\"a}ngen. Um die Ver{\"o}ffentlichung eines global frei verf{\"u}gbaren Onlinekurses abseits der großen MOOC Plattformen und den didaktischen Herausforderungen auch hinsichtlich der Motivation geht es im Beitrag von Ennio Marani und Isabel Jaisli. Schließlich schlagen Gregor Damnik et al. die automatische Erzeugung von Aufgaben zur Erh{\"o}hung von Interaktivit{\"a}t und Adaptivit{\"a}t in digitalen Lernressourcen vor, um den teilweise erheblichen Erstellungsaufwand zu reduzieren. Zum Thema E-Learning z{\"a}hlen auch immer mobile Apps bzw. Spiele. Gleich zwei Beitr{\"a}ge besch{\"a}ftigen sich mit dem Einsatz von E-Learning-Tools im Gesundheitskontext: Anna Tscherejkina und Anna Morgiel stellen in ihrem Beitrag Minispiele zum Training von sozio-emotionalen Kompetenzen f{\"u}r Menschen mit Autismus vor, und Stephanie Herbstreit et al. berichten vom Einsatz einer mobilen Lern-App zur Verbesserung von klinisch-praktischem Unterricht.}, language = {de} } @inproceedings{SeegererRomeikeTillmannetal.2018, author = {Seegerer, Stefan and Romeike, Ralf and Tillmann, Alexander and Kr{\"o}mker, Detlef and Horn, Florian and Gattinger, Thorsten and Weicker, Karsten and Schmitz, Dennis and Moldt, Daniel and R{\"o}pke, Ren{\´e} and Larisch, Kathrin and Schroeder, Ulrik and Keverp{\"u}tz, Claudia and K{\"u}ppers, Bastian and Striewe, Michael and Kramer, Matthias and Grillenberger, Andreas and Frede, Christiane and Knobelsdorf, Maria and Greven, Christoph}, title = {Hochschuldidaktik der Informatik HDI 2018}, series = {Commentarii informaticae didacticae (CID)}, booktitle = {Commentarii informaticae didacticae (CID)}, number = {12}, editor = {Bergner, Nadine and R{\"o}pke, Ren{\´e} and Schroeder, Ulrik and Kr{\"o}mker, Detlef}, publisher = {Universit{\"a}tsverlag Potsdam}, address = {Potsdam}, isbn = {978-3-86956-435-7}, issn = {1868-0844}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-413542}, pages = {161}, year = {2018}, abstract = {Die 8. Fachtagung f{\"u}r Hochschuldidaktik der Informatik (HDI) fand im September 2018 zusammen mit der Deutschen E-Learning Fachtagung Informatik (DeLFI) unter dem gemeinsamen Motto „Digitalisierungswahnsinn? - Wege der Bildungstransformationen" in Frankfurt statt. Dabei widmet sich die HDI allen Fragen der informatischen Bildung im Hochschulbereich. Schwerpunkte bildeten in diesem Jahr u. a.: - Analyse der Inhalte und anzustrebenden Kompetenzen in Informatikveranstaltungen - Programmieren lernen \& Einstieg in Softwareentwicklung - Spezialthemen: Data Science, Theoretische Informatik und Wissenschaftliches Arbeiten Die Fachtagung widmet sich ausgew{\"a}hlten Fragestellungen dieser Themenkomplexe, die durch Vortr{\"a}ge ausgewiesener Experten und durch eingereichte Beitr{\"a}ge intensiv behandelt werden.}, language = {de} } @article{TranPontelliBalduccinietal.2022, author = {Tran, Son Cao and Pontelli, Enrico and Balduccini, Marcello and Schaub, Torsten}, title = {Answer set planning}, series = {Theory and practice of logic programming}, journal = {Theory and practice of logic programming}, publisher = {Cambridge University Press}, address = {New York}, issn = {1471-0684}, doi = {10.1017/S1471068422000072}, pages = {73}, year = {2022}, abstract = {Answer Set Planning refers to the use of Answer Set Programming (ASP) to compute plans, that is, solutions to planning problems, that transform a given state of the world to another state. The development of efficient and scalable answer set solvers has provided a significant boost to the development of ASP-based planning systems. This paper surveys the progress made during the last two and a half decades in the area of answer set planning, from its foundations to its use in challenging planning domains. The survey explores the advantages and disadvantages of answer set planning. It also discusses typical applications of answer set planning and presents a set of challenges for future research.}, language = {en} } @phdthesis{Schapranow2012, author = {Schapranow, Matthieu-Patrick}, title = {Real-time security extensions for EPCglobal networks}, address = {Potsdam}, pages = {XVII, 108, XXX S.}, year = {2012}, language = {en} } @book{HoofReinke1999, author = {Hoof, Karsten and Reinke, Thomas}, title = {Entwurf und Realisierung einer komplexen verteilten Bankanwendung mit Hilfe der CORBA-Implementation Orbix}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, volume = {1999, 06}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, publisher = {Univ.}, address = {Potsdam}, issn = {0946-7580}, pages = {V, 75 S. : graph. Darst.}, year = {1999}, language = {de} } @article{StrickrothKiy2020, author = {Strickroth, Sven and Kiy, Alexander}, title = {E-Assessment etablieren}, series = {Potsdamer Beitr{\"a}ge zur Hochschulforschung}, journal = {Potsdamer Beitr{\"a}ge zur Hochschulforschung}, number = {6}, publisher = {Universit{\"a}tsverlag Potsdam}, address = {Potsdam}, isbn = {978-3-86956-498-2}, issn = {2192-1075}, doi = {10.25932/publishup-49303}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-493036}, pages = {257 -- 272}, year = {2020}, abstract = {Elektronische Lernstandserhebungen, sogenannte E-Assessments, bieten f{\"u}r Lehrende und Studierende viele Vorteile z. B. hinsichtlich schneller R{\"u}ckmeldungen oder kompetenzorientierter Fragenformate, und erm{\"o}glichen es, unabh{\"a}ngig von Ort und Zeit Pr{\"u}fungen zu absolvieren. In diesem Beitrag werden die Einf{\"u}hrung von summativen Lernstandserhebungen, sogenannter E-Klausuren, am Beispiel der Universit{\"a}t Potsdam, der Aufbau einer l{\"a}nder{\"u}bergreifenden Initiative f{\"u}r E-Assessment sowie technische M{\"o}glichkeiten f{\"u}r dezentrale elektronische Klausuren vorgestellt. Dabei werden der aktuelle Stand, die Ziele und die gew{\"a}hlte stufenweise Umsetzungsstrategie der Universit{\"a}t Potsdam skizziert. Darauf aufbauend folgt eine Beschreibung des Vorgehens, der Kooperationsm{\"o}glichkeiten f{\"u}r den Wissens- und Erfahrungsaustausch sowie Herausforderungen der E-Assessment- Initiative. Abschließend werden verschiedene E-Klausurformen und technische M{\"o}glichkeiten zur Umsetzung komplexer Pr{\"u}fungsumgebungen klassifiziert sowie mit ihren charakteristischen Vor- und Nachteilen diskutiert und eine integrierte L{\"o}sung vorgeschlagen.}, language = {de} } @article{LuckeStrickroth2020, author = {Lucke, Ulrike and Strickroth, Sven}, title = {Digitalisierung in Lehre und Studium}, series = {Potsdamer Beitr{\"a}ge zur Hochschulforschung}, journal = {Potsdamer Beitr{\"a}ge zur Hochschulforschung}, number = {6}, publisher = {Universit{\"a}tsverlag Potsdam}, address = {Potsdam}, isbn = {978-3-86956-498-2}, issn = {2192-1075}, doi = {10.25932/publishup-49302}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-493024}, pages = {235 -- 255}, year = {2020}, abstract = {Das gr{\"o}ßte der f{\"a}cher{\"u}bergreifenden Projekte im Potsdamer Projekt Qualit{\"a}tspakt Lehre hatte die fl{\"a}chendeckende Etablierung von digitalen Medien als einen integralen Bestandteil von Lehre und Studium zum Gegenstand. Im Teilprojekt E-Learning in Studienbereichen (eLiS) wurden daf{\"u}r Maßnahmen in den Feldern Organisations-, technische und Inhaltsentwicklung zusammengef{\"u}hrt. Der vorliegende Beitrag pr{\"a}sentiert auf Basis von Ausgangslage und Zielsetzungen die Ergebnisse rund um die Digitalisierung von Lehre und Studium an der Universit{\"a}t Potsdam. Exemplarisch werden f{\"u}nf Dienste n{\"a}her vorgestellt, die inzwischen gr{\"o}ßtenteils in den Regelbetrieb der Hochschule {\"u}bergegangen sind: die Videoplattform Media.UP, die mobile App Reflect.UP, die pers{\"o}nliche Lernumgebung Campus. UP, das Self-Service-Portal Cook.UP und das Anzeigesystem Freiraum.UP. Dabei wird jeweils ein technischer Blick „unter die Haube" verbunden mit einer Erl{\"a}uterung der Nutzungsm{\"o}glichkeiten, denen eine aktuelle Einsch{\"a}tzung von Lehrenden und Studierenden der Hochschule gegen{\"u}bergestellt wird. Der Beitrag schließt mit einer Einbettung der vorgestellten Entwicklungen in einen gr{\"o}ßeren Kontext und einem Ausblick auf die weiterhin anstehenden Aufgaben.}, language = {de} } @article{SchellSchwill2023, author = {Schell, Timon and Schwill, Andreas}, title = {„Es ist kompliziert, alles inklusive Privatleben unter einen Hut zu bekommen"}, series = {Hochschuldidaktik Informatik HDI 2021 (Commentarii informaticae didacticae)}, journal = {Hochschuldidaktik Informatik HDI 2021 (Commentarii informaticae didacticae)}, number = {13}, publisher = {Universit{\"a}tsverlag Potsdam}, address = {Potsdam}, isbn = {978-3-86956-548-4}, issn = {1868-0844}, doi = {10.25932/publishup-61388}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-613882}, pages = {53 -- 71}, year = {2023}, abstract = {Eine {\"u}bliche Erz{\"a}hlung verkn{\"u}pft lange Studienzeiten und hohe Abbrecherquoten im Informatikstudium zum einen mit der sehr gut bezahlten Nebent{\"a}tigkeit von Studierenden in der Informatikbranche, die deutlich studienzeitverl{\"a}ngernd sei; zum anderen werde wegen des hohen Bedarfs an Informatikern ein formeller Studienabschluss von den Studierenden h{\"a}ufig als entbehrlich betrachtet und eine Karriere in der Informatikbranche ohne abgeschlossenes Studium begonnen. In dieser Studie, durchgef{\"u}hrt an der Universit{\"a}t Potsdam, untersuchen wir, wie viele Informatikstudierende neben dem Studium innerhalb und außerhalb der Informatikbranche arbeiten, welche Erwartungen sie neben der Bezahlung damit verbinden und wie sich die T{\"a}tigkeit auf ihr Studium und ihre sp{\"a}tere berufliche Perspektive auswirkt. Aus aktuellem Anlass interessieren uns auch die Auswirkungen der Covid-19-Pandemie auf die Arbeitst{\"a}tigkeiten der Informatikstudierenden.}, language = {de} } @misc{Ziemann2024, type = {Master Thesis}, author = {Ziemann, Felix}, title = {Entwicklung und Evaluation einer prototypischen Lernumgebung f{\"u}r das systematische Debugging logischer Fehler in Quellcode}, doi = {10.25932/publishup-63273}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-632734}, school = {Universit{\"a}t Potsdam}, pages = {x, 98}, year = {2024}, abstract = {Wo programmiert wird, da passieren Fehler. Um das Debugging, also die Suche sowie die Behebung von Fehlern in Quellcode, st{\"a}rker explizit zu adressieren, verfolgt die vorliegende Arbeit das Ziel, entlang einer prototypischen Lernumgebung sowohl ein systematisches Vorgehen w{\"a}hrend des Debuggings zu vermitteln als auch Gestaltungsfolgerungen f{\"u}r ebensolche Lernumgebungen zu identifizieren. Dazu wird die folgende Forschungsfrage gestellt: Wie verhalten sich die Lernenden w{\"a}hrend des kurzzeitigen Gebrauchs einer Lernumgebung nach dem Cognitive Apprenticeship-Ansatz mit dem Ziel der expliziten Vermittlung eines systematischen Debuggingvorgehens und welche Eindr{\"u}cke entstehen w{\"a}hrend der Bearbeitung? Zur Beantwortung dieser Forschungsfrage wurde orientierend an literaturbasierten Implikationen f{\"u}r die Vermittlung von Debugging und (medien-)didaktischen Gestaltungsaspekten eine prototypische Lernumgebung entwickelt und im Rahmen einer qualitativen Nutzerstudie mit Bachelorstudierenden informatischer Studieng{\"a}nge erprobt. Hierbei wurden zum einen anwendungsbezogene Verbesserungspotenziale identifiziert. Zum anderen zeigte sich insbesondere gegen{\"u}ber der Systematisierung des Debuggingprozesses innerhalb der Aufgabenbearbeitung eine positive Resonanz. Eine Untersuchung, inwieweit sich die Nutzung der Lernumgebung l{\"a}ngerfristig auf das Verhalten von Personen und ihre Vorgehensweisen w{\"a}hrend des Debuggings auswirkt, k{\"o}nnte Gegenstand kommender Arbeiten sein.}, language = {de} } @article{BredeBotta2021, author = {Brede, Nuria and Botta, Nicola}, title = {On the correctness of monadic backward induction}, series = {Journal of functional programming}, volume = {31}, journal = {Journal of functional programming}, publisher = {Cambridge University Press}, address = {Cambridge}, issn = {1469-7653}, doi = {10.1017/S0956796821000228}, pages = {39}, year = {2021}, abstract = {In control theory, to solve a finite-horizon sequential decision problem (SDP) commonly means to find a list of decision rules that result in an optimal expected total reward (or cost) when taking a given number of decision steps. SDPs are routinely solved using Bellman's backward induction. Textbook authors (e.g. Bertsekas or Puterman) typically give more or less formal proofs to show that the backward induction algorithm is correct as solution method for deterministic and stochastic SDPs. Botta, Jansson and Ionescu propose a generic framework for finite horizon, monadic SDPs together with a monadic version of backward induction for solving such SDPs. In monadic SDPs, the monad captures a generic notion of uncertainty, while a generic measure function aggregates rewards. In the present paper, we define a notion of correctness for monadic SDPs and identify three conditions that allow us to prove a correctness result for monadic backward induction that is comparable to textbook correctness proofs for ordinary backward induction. The conditions that we impose are fairly general and can be cast in category-theoretical terms using the notion of Eilenberg-Moore algebra. They hold in familiar settings like those of deterministic or stochastic SDPs, but we also give examples in which they fail. Our results show that backward induction can safely be employed for a broader class of SDPs than usually treated in textbooks. However, they also rule out certain instances that were considered admissible in the context of Botta et al. 's generic framework. Our development is formalised in Idris as an extension of the Botta et al. framework and the sources are available as supplementary material.}, language = {en} } @book{NazajkinskijSavinSchulzeetal.2004, author = {Nazajkinskij, Vladimir E. and Savin, Anton and Schulze, Bert-Wolfgang and Sternin, Boris}, title = {Elliptic theory on manifolds with edges}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, publisher = {Univ.}, address = {Potsdam}, issn = {1437-739X}, pages = {48 S.}, year = {2004}, language = {en} } @book{FedosovSchulzeTarchanov2000, author = {Fedosov, Boris V. and Schulze, Bert-Wolfgang and Tarchanov, Nikolaj N.}, title = {Analytic index formulas for elliptic corner operators}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, publisher = {Univ.}, address = {Potsdam}, issn = {1437-739X}, pages = {70 S.}, year = {2000}, language = {en} } @book{EgorovKondratievSchulze2004, author = {Egorov, Yu. and Kondratiev, V. A. and Schulze, Bert-Wolfgang}, title = {On the completeness of root functions of elliptic boundary problems in a domain with conical points on the boundary}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, publisher = {Univ.}, address = {Potsdam}, issn = {1437-739X}, pages = {21 S.}, year = {2004}, language = {en} } @book{NazajkinskijSavinSchulzeetal.2004, author = {Nazajkinskij, Vladimir E. and Savin, Anton and Schulze, Bert-Wolfgang and Sternin, Boris}, title = {On the homotopy classification of elliptic operators on manifolds with edges}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, publisher = {Univ.}, address = {Potsdam}, issn = {1437-739X}, pages = {26 S.}, year = {2004}, language = {en} } @article{MichallekGenskeNiehuesetal.2022, author = {Michallek, Florian and Genske, Ulrich and Niehues, Stefan Markus and Hamm, Bernd and Jahnke, Paul}, title = {Deep learning reconstruction improves radiomics feature stability and discriminative power in abdominal CT imaging}, series = {European Radiology}, volume = {32}, journal = {European Radiology}, number = {7}, publisher = {Springer}, address = {New York}, issn = {1432-1084}, doi = {10.1007/s00330-022-08592-y}, pages = {4587 -- 4595}, year = {2022}, abstract = {Objectives To compare image quality of deep learning reconstruction (AiCE) for radiomics feature extraction with filtered back projection (FBP), hybrid iterative reconstruction (AIDR 3D), and model-based iterative reconstruction (FIRST). Methods Effects of image reconstruction on radiomics features were investigated using a phantom that realistically mimicked a 65-year-old patient's abdomen with hepatic metastases. The phantom was scanned at 18 doses from 0.2 to 4 mGy, with 20 repeated scans per dose. Images were reconstructed with FBP, AIDR 3D, FIRST, and AiCE. Ninety-three radiomics features were extracted from 24 regions of interest, which were evenly distributed across three tissue classes: normal liver, metastatic core, and metastatic rim. Features were analyzed in terms of their consistent characterization of tissues within the same image (intraclass correlation coefficient >= 0.75), discriminative power (Kruskal-Wallis test p value < 0.05), and repeatability (overall concordance correlation coefficient >= 0.75). Results The median fraction of consistent features across all doses was 6\%, 8\%, 6\%, and 22\% with FBP, AIDR 3D, FIRST, and AiCE, respectively. Adequate discriminative power was achieved by 48\%, 82\%, 84\%, and 92\% of features, and 52\%, 20\%, 17\%, and 39\% of features were repeatable, respectively. Only 5\% of features combined consistency, discriminative power, and repeatability with FBP, AIDR 3D, and FIRST versus 13\% with AiCE at doses above 1 mGy and 17\% at doses >= 3 mGy. AiCE was the only reconstruction technique that enabled extraction of higher-order features. Conclusions AiCE more than doubled the yield of radiomics features at doses typically used clinically. Inconsistent tissue characterization within CT images contributes significantly to the poor stability of radiomics features.}, language = {en} } @book{HarutjunjanSchulze2004, author = {Harutjunjan, Gohar and Schulze, Bert-Wolfgang}, title = {Boundary problems with meromorphic symbols in cylindrical domains}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, publisher = {Univ.}, address = {Potsdam}, issn = {1437-739X}, pages = {19 S.}, year = {2004}, language = {en} } @book{LiuSchulze2004, author = {Liu, Xiaochun and Schulze, Bert-Wolfgang}, title = {Boundary value problems in edge representation}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, publisher = {Univ.}, address = {Potsdam}, issn = {1437-739X}, pages = {43 S.}, year = {2004}, language = {en} } @article{DinesLiuSchulze2009, author = {Dines, Nicoleta and Liu, Xiaochun and Schulze, Bert-Wolfgang}, title = {Edge quantisation of elliptic operators}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Mathematik, Arbeitsgruppe Partiell}, issn = {1437-739X}, doi = {10.1007/s00605-008-0058-y}, year = {2009}, abstract = {The ellipticity of operators on a manifold with edge is defined as the bijectivity of the components of a principal symbolic hierarchy sigma = (sigma(psi), sigma(boolean AND)), where the second component takes values in operators on the infinite model cone of the local wedges. In the general understanding of edge problems there are two basic aspects: Quantisation of edge-degenerate operators in weighted Sobolev spaces, and verifying the ellipticity of the principal edge symbol sigma(boolean AND) which includes the (in general not explicity known) number of additional conditions of trace and potential type on the edge. We focus here on these questions and give explicit answers for a wide class of elliptic operators that are connected with the ellipticity of edge boundary value problems and reductions to the boundary. In particular, we study the edge quantisation and ellipticity for Dirichlet-Neumann operators with respect to interfaces of some codimension on a boundary. We show analogues of the Agranovich-Dynin formula for edge boundary value problems.}, language = {en} } @article{BandyopadhyaySarkarMandaletal.2022, author = {Bandyopadhyay, Soumyadip and Sarkar, Dipankar and Mandal, Chittaranjan and Giese, Holger}, title = {Translation validation of coloured Petri net models of programs on integers}, series = {Acta informatica}, volume = {59}, journal = {Acta informatica}, number = {6}, publisher = {Springer}, address = {New York}, issn = {0001-5903}, doi = {10.1007/s00236-022-00419-z}, pages = {725 -- 759}, year = {2022}, abstract = {Programs are often subjected to significant optimizing and parallelizing transformations based on extensive dependence analysis. Formal validation of such transformations needs modelling paradigms which can capture both control and data dependences in the program vividly. Being value-based with an inherent scope of capturing parallelism, the untimed coloured Petri net (CPN) models, reported in the literature, fit the bill well; accordingly, they are likely to be more convenient as the intermediate representations (IRs) of both the source and the transformed codes for translation validation than strictly sequential variable-based IRs like sequential control flow graphs (CFGs). In this work, an efficient path-based equivalence checking method for CPN models of programs on integers is presented. Extensive experimentation has been carried out on several sequential and parallel examples. Complexity and correctness issues have been treated rigorously for the method.}, language = {en} } @article{OmranianMuellerRoeberNikoloski2015, author = {Omranian, Nooshin and M{\"u}ller-R{\"o}ber, Bernd and Nikoloski, Zoran}, title = {Segmentation of biological multivariate time-series data}, series = {Scientific reports}, volume = {5}, journal = {Scientific reports}, publisher = {Nature Publ. Group}, address = {London}, issn = {2045-2322}, doi = {10.1038/srep08937}, pages = {6}, year = {2015}, abstract = {Time-series data from multicomponent systems capture the dynamics of the ongoing processes and reflect the interactions between the components. The progression of processes in such systems usually involves check-points and events at which the relationships between the components are altered in response to stimuli. Detecting these events together with the implicated components can help understand the temporal aspects of complex biological systems. Here we propose a regularized regression-based approach for identifying breakpoints and corresponding segments from multivariate time-series data. In combination with techniques from clustering, the approach also allows estimating the significance of the determined breakpoints as well as the key components implicated in the emergence of the breakpoints. Comparative analysis with the existing alternatives demonstrates the power of the approach to identify biologically meaningful breakpoints in diverse time-resolved transcriptomics data sets from the yeast Saccharomyces cerevisiae and the diatom Thalassiosira pseudonana.}, language = {en} } @phdthesis{SchulzHanke2023, author = {Schulz-Hanke, Christian}, title = {BCH Codes mit kombinierter Korrektur und Erkennung}, doi = {10.25932/publishup-61794}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-617943}, school = {Universit{\"a}t Potsdam}, pages = {ii, 191}, year = {2023}, abstract = {BCH Codes mit kombinierter Korrektur und Erkennung In dieser Arbeit wird auf Grundlage des BCH Codes untersucht, wie eine Fehlerkorrektur mit einer Erkennung h{\"o}herer Fehleranzahlen kombiniert werden kann. Mit dem Verfahren der 1-Bit Korrektur mit zus{\"a}tzlicher Erkennung h{\"o}herer Fehler wurde ein Ansatz entwickelt, welcher die Erkennung zus{\"a}tzlicher Fehler durch das parallele L{\"o}sen einfacher Gleichungen der Form s_x = s_1^x durchf{\"u}hrt. Die Anzahl dieser Gleichungen ist linear zu der Anzahl der zu {\"u}berpr{\"u}fenden h{\"o}heren Fehler. In dieser Arbeit wurde zus{\"a}tzlich f{\"u}r bis zu 4-Bit Korrekturen mit zus{\"a}tzlicher Erkennung h{\"o}herer Fehler ein weiterer allgemeiner Ansatz vorgestellt. Dabei werden parallel f{\"u}r alle korrigierbaren Fehleranzahlen spekulative Fehlerkorrekturen durchgef{\"u}hrt. Aus den bestimmten Fehlerstellen werden spekulative Syndromkomponenten erzeugt, durch welche die Fehlerstellen best{\"a}tigt und h{\"o}here erkennbare Fehleranzahlen ausgeschlossen werden k{\"o}nnen. Die vorgestellten Ans{\"a}tze unterscheiden sich von dem in entwickelten Ansatz, bei welchem die Anzahl der Fehlerstellen durch die Berechnung von Determinanten in absteigender Reihenfolge berechnet wird, bis die erste Determinante 0 bildet. Bei dem bekannten Verfahren ist durch die Berechnung der Determinanten eine faktorielle Anzahl an Berechnungen in Relation zu der Anzahl zu {\"u}berpr{\"u}fender Fehler durchzuf{\"u}hren. Im Vergleich zu dem bekannten sequentiellen Verfahrens nach Berlekamp Massey besitzen die Berechnungen im vorgestellten Ansatz simple Gleichungen und k{\"o}nnen parallel durchgef{\"u}hrt werden.Bei dem bekannten Verfahren zur parallelen Korrektur von 4-Bit Fehlern ist eine Gleichung vierten Grades im GF(2^m) zu l{\"o}sen. Dies erfolgt, indem eine Hilfsgleichung dritten Grades und vier Gleichungen zweiten Grades parallel gel{\"o}st werden. In der vorliegenden Arbeit wurde gezeigt, dass sich eine Gleichung zweiten Grades einsparen l{\"a}sst, wodurch sich eine Vereinfachung der Hardware bei einer parallelen Realisierung der 4-Bit Korrektur ergibt. Die erzielten Ergebnisse wurden durch umfangreiche Simulationen in Software und Hardwareimplementierungen {\"u}berpr{\"u}ft.}, language = {de} } @article{ChenLangeAndjelkovicetal.2022, author = {Chen, Junchao and Lange, Thomas and Andjelkovic, Marko and Simevski, Aleksandar and Lu, Li and Krstić, Miloš}, title = {Solar particle event and single event upset prediction from SRAM-based monitor and supervised machine learning}, series = {IEEE transactions on emerging topics in computing / IEEE Computer Society, Institute of Electrical and Electronics Engineers}, volume = {10}, journal = {IEEE transactions on emerging topics in computing / IEEE Computer Society, Institute of Electrical and Electronics Engineers}, number = {2}, publisher = {Institute of Electrical and Electronics Engineers}, address = {[New York, NY]}, issn = {2168-6750}, doi = {10.1109/TETC.2022.3147376}, pages = {564 -- 580}, year = {2022}, abstract = {The intensity of cosmic radiation may differ over five orders of magnitude within a few hours or days during the Solar Particle Events (SPEs), thus increasing for several orders of magnitude the probability of Single Event Upsets (SEUs) in space-borne electronic systems. Therefore, it is vital to enable the early detection of the SEU rate changes in order to ensure timely activation of dynamic radiation hardening measures. In this paper, an embedded approach for the prediction of SPEs and SRAM SEU rate is presented. The proposed solution combines the real-time SRAM-based SEU monitor, the offline-trained machine learning model and online learning algorithm for the prediction. With respect to the state-of-the-art, our solution brings the following benefits: (1) Use of existing on-chip data storage SRAM as a particle detector, thus minimizing the hardware and power overhead, (2) Prediction of SRAM SEU rate one hour in advance, with the fine-grained hourly tracking of SEU variations during SPEs as well as under normal conditions, (3) Online optimization of the prediction model for enhancing the prediction accuracy during run-time, (4) Negligible cost of hardware accelerator design for the implementation of selected machine learning model and online learning algorithm. The proposed design is intended for a highly dependable and self-adaptive multiprocessing system employed in space applications, allowing to trigger the radiation mitigation mechanisms before the onset of high radiation levels.}, language = {en} } @article{AndjelkovićChenSimevskietal.2021, author = {Andjelković, Marko and Chen, Junchao and Simevski, Aleksandar and Schrape, Oliver and Krstić, Miloš and Kraemer, Rolf}, title = {Monitoring of particle count rate and LET variations with pulse stretching inverters}, series = {IEEE transactions on nuclear science : a publication of the IEEE Nuclear and Plasma Sciences Society}, volume = {68}, journal = {IEEE transactions on nuclear science : a publication of the IEEE Nuclear and Plasma Sciences Society}, number = {8}, publisher = {Institute of Electrical and Electronics Engineers}, address = {New York, NY}, issn = {0018-9499}, doi = {10.1109/TNS.2021.3076400}, pages = {1772 -- 1781}, year = {2021}, abstract = {This study investigates the use of pulse stretching (skew-sized) inverters for monitoring the variation of count rate and linear energy transfer (LET) of energetic particles. The basic particle detector is a cascade of two pulse stretching inverters, and the required sensing area is obtained by connecting up to 12 two-inverter cells in parallel and employing the required number of parallel arrays. The incident particles are detected as single-event transients (SETs), whereby the SET count rate denotes the particle count rate, while the SET pulsewidth distribution depicts the LET variations. The advantage of the proposed solution is the possibility to sense the LET variations using fully digital processing logic. SPICE simulations conducted on IHP's 130-nm CMOS technology have shown that the SET pulsewidth varies by approximately 550 ps over the LET range from 1 to 100 MeV center dot cm(2) center dot mg(-1). The proposed detector is intended for triggering the fault-tolerant mechanisms within a self-adaptive multiprocessing system employed in space. It can be implemented as a standalone detector or integrated in the same chip with the target system.}, language = {en} } @article{DimitrievSaposhnikovGoesseletal.1997, author = {Dimitriev, Alexej and Saposhnikov, Vl. V. and G{\"o}ssel, Michael and Saposhnikov, V. V.}, title = {On-line testing by self-dual duplication}, year = {1997}, language = {en} } @article{SaposhnikovMorosovSaposhnikovetal.1998, author = {Saposhnikov, V. V. and Morosov, Andrej and Saposhnikov, Vl. V. and G{\"o}ssel, Michael}, title = {A new design method for self-checking unidirectional combinational circuits}, year = {1998}, language = {en} } @article{SeuringGoesselSogomonyan1998, author = {Seuring, Markus and G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {A structural approach for space compaction for concurrent checking and BIST}, year = {1998}, language = {en} } @article{SogomonyanGoessel1995, author = {Sogomonyan, Egor S. and G{\"o}ssel, Michael}, title = {A new parity preserving multi-input signature analyser}, year = {1995}, language = {en} } @article{SaposhnikovMorosovSaposhnikovetal.1996, author = {Saposhnikov, Va. V. and Morosov, Andrej and Saposhnikov, Vl. V. and G{\"o}ssel, Michael}, title = {Design of self-checking unidirectional combinational circuits with low area overhead}, year = {1996}, language = {en} } @book{SaposhnikovSaposhnikovMorozovetal.2004, author = {Saposhnikov, V. V. and Saposhnikov, Vl. V. and Morozov, Alexei and G{\"o}ssel, Michael}, title = {Necessary and Sufficient Conditions for the Existence of Self-Checking Circuits ba Use of Complementary Circuits}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, volume = {2004, 1}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, publisher = {Univ.}, address = {Potsdam}, issn = {0946-7580}, pages = {11 S.}, year = {2004}, language = {en} } @phdthesis{Andjelkovic2021, author = {Andjelkovic, Marko}, title = {A methodology for characterization, modeling and mitigation of single event transient effects in CMOS standard combinational cells}, doi = {10.25932/publishup-53484}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-534843}, school = {Universit{\"a}t Potsdam}, pages = {xxiv, 216}, year = {2021}, abstract = {With the downscaling of CMOS technologies, the radiation-induced Single Event Transient (SET) effects in combinational logic have become a critical reliability issue for modern integrated circuits (ICs) intended for operation under harsh radiation conditions. The SET pulses generated in combinational logic may propagate through the circuit and eventually result in soft errors. It has thus become an imperative to address the SET effects in the early phases of the radiation-hard IC design. In general, the soft error mitigation solutions should accommodate both static and dynamic measures to ensure the optimal utilization of available resources. An efficient soft-error-aware design should address synergistically three main aspects: (i) characterization and modeling of soft errors, (ii) multi-level soft error mitigation, and (iii) online soft error monitoring. Although significant results have been achieved, the effectiveness of SET characterization methods, accuracy of predictive SET models, and efficiency of SET mitigation measures are still critical issues. Therefore, this work addresses the following topics: (i) Characterization and modeling of SET effects in standard combinational cells, (ii) Static mitigation of SET effects in standard combinational cells, and (iii) Online particle detection, as a support for dynamic soft error mitigation. Since the standard digital libraries are widely used in the design of radiation-hard ICs, the characterization of SET effects in standard cells and the availability of accurate SET models for the Soft Error Rate (SER) evaluation are the main prerequisites for efficient radiation-hard design. This work introduces an approach for the SPICE-based standard cell characterization with the reduced number of simulations, improved SET models and optimized SET sensitivity database. It has been shown that the inherent similarities in the SET response of logic cells for different input levels can be utilized to reduce the number of required simulations. Based on characterization results, the fitting models for the SET sensitivity metrics (critical charge, generated SET pulse width and propagated SET pulse width) have been developed. The proposed models are based on the principle of superposition, and they express explicitly the dependence of the SET sensitivity of individual combinational cells on design, operating and irradiation parameters. In contrast to the state-of-the-art characterization methodologies which employ extensive look-up tables (LUTs) for storing the simulation results, this work proposes the use of LUTs for storing the fitting coefficients of the SET sensitivity models derived from the characterization results. In that way the amount of characterization data in the SET sensitivity database is reduced significantly. The initial step in enhancing the robustness of combinational logic is the application of gate-level mitigation techniques. As a result, significant improvement of the overall SER can be achieved with minimum area, delay and power overheads. For the SET mitigation in standard cells, it is essential to employ the techniques that do not require modifying the cell structure. This work introduces the use of decoupling cells for improving the robustness of standard combinational cells. By insertion of two decoupling cells at the output of a target cell, the critical charge of the cell's output node is increased and the attenuation of short SETs is enhanced. In comparison to the most common gate-level techniques (gate upsizing and gate duplication), the proposed approach provides better SET filtering. However, as there is no single gate-level mitigation technique with optimal performance, a combination of multiple techniques is required. This work introduces a comprehensive characterization of gate-level mitigation techniques aimed to quantify their impact on the SET robustness improvement, as well as introduced area, delay and power overhead per gate. By characterizing the gate-level mitigation techniques together with the standard cells, the required effort in subsequent SER analysis of a target design can be reduced. The characterization database of the hardened standard cells can be utilized as a guideline for selection of the most appropriate mitigation solution for a given design. As a support for dynamic soft error mitigation techniques, it is important to enable the online detection of energetic particles causing the soft errors. This allows activating the power-greedy fault-tolerant configurations based on N-modular redundancy only at the high radiation levels. To enable such a functionality, it is necessary to monitor both the particle flux and the variation of particle LET, as these two parameters contribute significantly to the system SER. In this work, a particle detection approach based on custom-sized pulse stretching inverters is proposed. Employing the pulse stretching inverters connected in parallel enables to measure the particle flux in terms of the number of detected SETs, while the particle LET variations can be estimated from the distribution of SET pulse widths. This approach requires a purely digital processing logic, in contrast to the standard detectors which require complex mixed-signal processing. Besides the possibility of LET monitoring, additional advantages of the proposed particle detector are low detection latency and power consumption, and immunity to error accumulation. The results achieved in this thesis can serve as a basis for establishment of an overall soft-error-aware database for a given digital library, and a comprehensive multi-level radiation-hard design flow that can be implemented with the standard IC design tools. The following step will be to evaluate the achieved results with the irradiation experiments.}, language = {en} } @article{SchrapeAndjelkovicBreitenreiteretal.2021, author = {Schrape, Oliver and Andjelkovic, Marko and Breitenreiter, Anselm and Zeidler, Steffen and Balashov, Alexey and Krstić, Miloš}, title = {Design and evaluation of radiation-hardened standard cell flip-flops}, series = {IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers}, volume = {68}, journal = {IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers}, number = {11}, publisher = {Inst. of Electr. and Electronics Engineers}, address = {New York, NY}, issn = {1549-8328}, doi = {10.1109/TCSI.2021.3109080}, pages = {4796 -- 4809}, year = {2021}, abstract = {Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant.}, language = {en} } @article{BreitenreiterAndjelkovićSchrapeetal.2022, author = {Breitenreiter, Anselm and Andjelković, Marko and Schrape, Oliver and Krstić, Miloš}, title = {Fast error propagation probability estimates by answer set programming and approximate model counting}, series = {IEEE Access}, volume = {10}, journal = {IEEE Access}, publisher = {Inst. of Electr. and Electronics Engineers}, address = {Piscataway}, issn = {2169-3536}, doi = {10.1109/ACCESS.2022.3174564}, pages = {51814 -- 51825}, year = {2022}, abstract = {We present a method employing Answer Set Programming in combination with Approximate Model Counting for fast and accurate calculation of error propagation probabilities in digital circuits. By an efficient problem encoding, we achieve an input data format similar to a Verilog netlist so that extensive preprocessing is avoided. By a tight interconnection of our application with the underlying solver, we avoid iterating over fault sites and reduce calls to the solver. Several circuits were analyzed with varying numbers of considered cycles and different degrees of approximation. Our experiments show, that the runtime can be reduced by approximation by a factor of 91, whereas the error compared to the exact result is below 1\%.}, language = {en} } @article{GoesselSogomonyan1996, author = {G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {A parity-preserving multi-input signature analyzer and it application for concurrent checking and BIST}, year = {1996}, language = {en} } @article{LiChenNofaletal.2018, author = {Li, Yuanqing and Chen, Li and Nofal, Issam and Chen, Mo and Wang, Haibin and Liu, Rui and Chen, Qingyu and Krstić, Miloš and Shi, Shuting and Guo, Gang and Baeg, Sang H. and Wen, Shi-Jie and Wong, Richard}, title = {Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree}, series = {Microelectronics reliability}, volume = {87}, journal = {Microelectronics reliability}, publisher = {Elsevier}, address = {Oxford}, issn = {0026-2714}, doi = {10.1016/j.microrel.2018.05.016}, pages = {24 -- 32}, year = {2018}, abstract = {The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.}, language = {en} } @article{MorosovSaposhnikovSaposhnikovetal.1997, author = {Morosov, Andrej and Saposhnikov, Vl. V. and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Design of self dual fault-secure combinational circuits}, year = {1997}, language = {en} } @article{SaposhnikovSaposhnikovDimitrievetal.1998, author = {Saposhnikov, Vl. V. and Saposhnikov, V. V. and Dimitriev, Alexej and G{\"o}ssel, Michael}, title = {Self-dual duplication for error detection}, year = {1998}, language = {en} } @article{SeuringGoessel1999, author = {Seuring, Markus and G{\"o}ssel, Michael}, title = {A structural approach for space compaction for sequential circuits}, year = {1999}, language = {en} } @article{HartjeGoesselSogomonyan1997, author = {Hartje, Hendrik and G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {Synthesis of code-disjoint combinational circuits}, year = {1997}, language = {en} } @phdthesis{Weidling2016, author = {Weidling, Stefan}, title = {Neue Ans{\"a}tze zur Verbesserung der Fehlertoleranz gegen{\"u}ber transienten Fehlern in sequentiellen Schaltungen}, school = {Universit{\"a}t Potsdam}, pages = {XII, 181}, year = {2016}, language = {de} } @misc{KrstićJentzsch2018, author = {Krstić, Miloš and Jentzsch, Anne-Kristin}, title = {Reliability, safety and security of the electronics in automated driving vehicles - joint lab lecturing approach}, series = {2018 12TH European Workshop on Microelectronics Education (EWME)}, journal = {2018 12TH European Workshop on Microelectronics Education (EWME)}, publisher = {IEEE}, address = {New York}, isbn = {978-1-5386-1157-9}, pages = {21 -- 22}, year = {2018}, abstract = {This paper proposes an education approach for master and bachelor students to enhance their skills in the area of reliability, safety and security of the electronic components in automated driving. The approach is based on the active synergetic work of research institutes, academia and industry in the frame of joint lab. As an example, the jointly organized summer school with the respective focus is organized and elaborated.}, language = {en} } @article{SinghSogomonyanGoesseletal.1999, author = {Singh, Adit D. and Sogomonyan, Egor S. and G{\"o}ssel, Michael and Seuring, Markus}, title = {Testability evaluation of sequential designs incorporating the multi-mode scannable memory element}, year = {1999}, language = {en} } @article{SaposhnikovSaposhnikovGoesseletal.1999, author = {Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael and Morosov, Andrej}, title = {A method of construction of combinational self-checking units with detection of all single faults}, year = {1999}, language = {en} } @article{GoesselSogomonyan1994, author = {G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {Self-parity combinational-circuits for self-testing, concurrent fault-detection and parity scan design}, year = {1994}, language = {en} } @article{GoesselSogomonyanMorosov1999, author = {G{\"o}ssel, Michael and Sogomonyan, Egor S. and Morosov, Andrej}, title = {A new totally error propagating compactor for arbitrary cores with digital interfaces}, year = {1999}, language = {en} } @article{GoesselMorosovSaposhnikovetal.1994, author = {G{\"o}ssel, Michael and Morosov, Andrej and Saposhnikov, V. V. and Saposhnikov, VL. V.}, title = {Design of combinational self-testing devices with unidirectionally independent outputs}, year = {1994}, language = {en} } @book{MarienfeldSogomonyanOcheretnijetal.2005, author = {Marienfeld, Daniel and Sogomonyan, Egor S. and Ocheretnij, V. and G{\"o}ssel, Michael}, title = {Self-checking Output-duplicated Booth-2 Multiplier}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, volume = {2005, 1}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, publisher = {Univ.}, address = {Potsdam}, issn = {0946-7580}, year = {2005}, language = {en} } @article{SogomonyanSinghGoessel1998, author = {Sogomonyan, Egor S. and Singh, Adit D. and G{\"o}ssel, Michael}, title = {A scan based concrrent BIST approach for low cost on-line testing}, year = {1998}, language = {en} } @book{SogomonyanMarienfeldGoessel2006, author = {Sogomonyan, Egor S. and Marienfeld, Daniel and G{\"o}ssel, Michael}, title = {Fehlerkorrektur und Fehlererkennung}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, volume = {2006, 3}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, publisher = {Univ.}, address = {Potsdam}, issn = {0946-7580}, pages = {31, 8 S.}, year = {2006}, language = {de} } @phdthesis{Niess2016, author = {Nieß, G{\"u}nther}, title = {Modellierung und Erkennung von technischen Fehlern mittels linearer und nichtlinearer Codes}, school = {Universit{\"a}t Potsdam}, pages = {V, 97}, year = {2016}, language = {de} } @book{BoernerGoessel2005, author = {B{\"o}rner, Ferdinand and G{\"o}ssel, Michael}, title = {Grundlagen digitaler Systeme}, publisher = {Univ.-Verl.}, address = {Potsdam}, isbn = {978-3-937786-46-9}, pages = {95 S.}, year = {2005}, language = {de} } @article{DmitrievSaposhnikovSaposhnikovetal.1999, author = {Dmitriev, Alexej and Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael}, title = {Self-dual sequential circuits for concurrent chechking}, isbn = {0-7695-0390-X ; 0-7695-0391-8}, year = {1999}, language = {en} } @book{SogomonyanMarienfeldOcheretnijetal.2003, author = {Sogomonyan, Egor S. and Marienfeld, Daniel and Ocheretnij, V. and G{\"o}ssel, Michael}, title = {A new self-checking sum-bit duplicated carry-select adder}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, volume = {2003, 5}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, publisher = {Univ.}, address = {Potsdam}, issn = {0946-7580}, pages = {10 S.}, year = {2003}, language = {en} } @article{SogomonyanSinghGoessel1999, author = {Sogomonyan, Egor S. and Singh, Adit D. and G{\"o}ssel, Michael}, title = {A multi-mode scannable memory element for high test application efficiency and delay testing}, year = {1999}, language = {en} } @book{WuKarriKuznetsovetal.2003, author = {Wu, K. and Karri, R. and Kuznetsov, Grigory and G{\"o}ssel, Michael}, title = {Low Cost Concurrent Error Detection for the Advanced Encryption Standart}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, volume = {2003, 8}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, publisher = {Univ.}, address = {Potsdam}, issn = {0946-7580}, pages = {10 S.}, year = {2003}, language = {en} } @book{BoernerGoessel2001, author = {B{\"o}rner, Ferdinand and G{\"o}ssel, Michael}, title = {Grundlagen digitaler Systeme}, editor = {G{\"o}ssel, Michael}, publisher = {Univ.-Bibliothek Publ.-Stelle}, address = {Potsdam}, isbn = {3-935024-34-7}, pages = {95 S. : graph. Darst.}, year = {2001}, language = {de} } @book{SapoznikovSapoznikovGoessel2001, author = {Sapoznikov, V. V. and Sapoznikov, VL. V. and G{\"o}ssel, Michael}, title = {Samodvojstvennye diskretnye ustrojstva}, publisher = {?nergoatomizdat}, address = {Sankt-Peterburg}, isbn = {5-283-04748-2}, pages = {330 S.}, year = {2001}, language = {ru} } @book{BoernerGoessel2000, author = {B{\"o}rner, Ferdinand and G{\"o}ssel, Michael}, title = {Grundlagen digitaler Systeme}, publisher = {Univ.-Bibliothek Publ.-Stelle}, address = {Potsdam}, isbn = {3-9806494-9-0}, pages = {61 S.}, year = {2000}, language = {de} } @article{OcheretnijGoesselSogomonyanetal.2006, author = {Ocheretnij, Vitalij and G{\"o}ssel, Michael and Sogomonyan, Egor S. and Marienfeld, Daniel}, title = {Modulo p=3 checking for a carry select adder}, doi = {10.1007/s10836-006-6260-8}, year = {2006}, abstract = {In this paper a self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20\%. No restrictions are imposed on the design of the adder blocks}, language = {en} } @article{OtscheretnijSaposhnikovSaposhnikovetal.1999, author = {Otscheretnij, Vitalij and Saposhnikov, Vl. V. and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Fault-tolerant self-dual circuits}, year = {1999}, language = {en} } @article{SaposhnikovMoshaninSaposhnikovetal.1999, author = {Saposhnikov, Vl. V. V. V. and Moshanin, Vl. and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Experimental results for self-dual multi-output combinational circuits}, year = {1999}, language = {en} } @article{GoesselDimitrievSaposhnikovetal.1999, author = {G{\"o}ssel, Michael and Dimitriev, Alexej and Saposhnikov, V. V. and Saposhnikov, Vl. V.}, title = {Eine selbsttestende Struktur zur on-line Fehlererkennung in kombinatorischen Schaltungen}, year = {1999}, language = {de} } @article{SaposhnikovOcheretnijSaposhnikovetal.1999, author = {Saposhnikov, Vl. V. and Ocheretnij, V. and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Modified TMR-system with reduced hardware overhead}, year = {1999}, language = {en} } @article{GoesselSogomonyan1999, author = {G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {New totally self-checking ripple and carry look-ahead adders}, year = {1999}, language = {en} } @article{Goessel1999, author = {G{\"o}ssel, Michael}, title = {A new method of redundancy addition for circuit optimization}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, volume = {1999, 08}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, publisher = {Univ.}, address = {Potsdam}, issn = {0946-7580}, pages = {9 Bl.}, year = {1999}, language = {en} } @article{BogueJuergensenGoessel1994, author = {Bogue, Ted and J{\"u}rgensen, Helmut and G{\"o}ssel, Michael}, title = {Design of cover circuits for monitoring the output of a MISR}, isbn = {0-8186-6307-3 , 0-8186-6306-5}, year = {1994}, language = {en} } @article{MorosovSaposhnikovSaposhnikovetal.1997, author = {Morosov, Andrej and Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael}, title = {Ein Transformationsalgorithmus einer kombinatorischen Schaltung in eine monotone Schaltung}, year = {1997}, language = {de} } @article{SaposhnikovDimitrievGoesseletal.1996, author = {Saposhnikov, Vl. V. and Dimitriev, Alexej and G{\"o}ssel, Michael and Saposhnikov, Va. V.}, title = {Self-dual parity checking - a new method for on-line testing}, year = {1996}, language = {en} } @article{GoesselSogomonyan1994, author = {G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design}, year = {1994}, language = {en} } @article{KunduSogomonyanGoesseletal.1996, author = {Kundu, S. and Sogomonyan, Egor S. and G{\"o}ssel, Michael and Tarnick, Steffen}, title = {Self-checking comparator with one periodiv output}, year = {1996}, language = {en} } @article{HartjeSogomonyanGoessel1997, author = {Hartje, Hendrik and Sogomonyan, Egor S. and G{\"o}ssel, Michael}, title = {Code disjoint circuits for partity codes}, year = {1997}, language = {en} } @article{BogueJuergensenGoessel1995, author = {Bogue, Ted and J{\"u}rgensen, Helmut and G{\"o}ssel, Michael}, title = {BIST with negligible aliasing through random cover circuits}, year = {1995}, language = {en} } @article{RabenaltRichterPoehletal.2012, author = {Rabenalt, Thomas and Richter, Michael and P{\"o}hl, Frank and G{\"o}ssel, Michael}, title = {Highly efficient test response compaction using a hierarchical x-masking technique}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, volume = {31}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, number = {6}, publisher = {Inst. of Electr. and Electronics Engineers}, address = {Piscataway}, issn = {0278-0070}, doi = {10.1109/TCAD.2011.2181847}, pages = {950 -- 957}, year = {2012}, abstract = {This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.}, language = {en} } @article{DugWeidlingSogomonyanetal.2020, author = {Dug, Mehmed and Weidling, Stefan and Sogomonyan, Egor and Jokic, Dejan and Krstić, Miloš}, title = {Full error detection and correction method applied on pipelined structure using two approaches}, series = {Journal of circuits, systems and computers}, volume = {29}, journal = {Journal of circuits, systems and computers}, number = {13}, publisher = {World Scientific}, address = {Singapore}, issn = {0218-1266}, doi = {10.1142/S0218126620502187}, pages = {15}, year = {2020}, abstract = {In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.}, language = {en} } @article{LiBreitenreiterAndjelkovicetal.2020, author = {Li, Yuanqing and Breitenreiter, Anselm and Andjelkovic, Marko and Chen, Junchao and Babic, Milan and Krstić, Miloš}, title = {Double cell upsets mitigation through triple modular redundancy}, series = {Microelectronics Journal}, volume = {96}, journal = {Microelectronics Journal}, publisher = {Elsevier}, address = {Oxford}, issn = {0026-2692}, doi = {10.1016/j.mejo.2019.104683}, pages = {8}, year = {2020}, abstract = {A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3\% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.}, language = {en} } @phdthesis{Hosp2015, author = {Hosp, Sven}, title = {Modifizierte Cross-Party Codes zur schnellen Mehrbit-Fehlerkorrektur}, pages = {105}, year = {2015}, language = {de} } @article{AndjelkovicSimevskiChenetal.2022, author = {Andjelkovic, Marko and Simevski, Aleksandar and Chen, Junchao and Schrape, Oliver and Stamenkovic, Zoran and Krstić, Miloš and Ilic, Stefan and Ristic, Goran and Jaksic, Aleksandar and Vasovic, Nikola and Duane, Russell and Palma, Alberto J. and Lallena, Antonio M. and Carvajal, Miguel A.}, title = {A design concept for radiation hardened RADFET readout system for space applications}, series = {Microprocessors and microsystems}, volume = {90}, journal = {Microprocessors and microsystems}, publisher = {Elsevier}, address = {Amsterdam}, issn = {0141-9331}, doi = {10.1016/j.micpro.2022.104486}, pages = {18}, year = {2022}, abstract = {Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET's response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions.}, language = {en} } @article{RisticIlicAndjelkovicetal.2022, author = {Ristic, Goran S. and Ilic, Stefan D. and Andjelkovic, Marko S. and Duane, Russell and Palma, Alberto J. and Lalena, Antonio M. and Krstić, Miloš and Jaksic, Aleksandar B.}, title = {Sensitivity and fading of irradiated RADFETs with different gate voltages}, series = {Nuclear Instruments and Methods in Physics Research Section A}, volume = {1029}, journal = {Nuclear Instruments and Methods in Physics Research Section A}, publisher = {Elsevier}, address = {Amsterdam}, issn = {0168-9002}, doi = {10.1016/j.nima.2022.166473}, pages = {7}, year = {2022}, abstract = {The radiation-sensitive field-effect transistors (RADFETs) with an oxide thickness of 400 nm are irradiated with gate voltages of 2, 4 and 6 V, and without gate voltage. A detailed analysis of the mechanisms responsible for the creation of traps during irradiation is performed. The creation of the traps in the oxide, near and at the silicon/silicon-dioxide (Si/SiO2) interface during irradiation is modelled very well. This modelling can also be used for other MOS transistors containing SiO2. The behaviour of radiation traps during postirradiation annealing is analysed, and the corresponding functions for their modelling are obtained. The switching traps (STs) do not have significant influence on threshold voltage shift, and two radiation-induced trap types fit the fixed traps (FTs) very well. The fading does not depend on the positive gate voltage applied during irradiation, but it is twice lower in case there is no gate voltage. A new dosimetric parameter, called the Golden Ratio (GR), is proposed, which represents the ratio between the threshold voltage shift after irradiation and fading after spontaneous annealing. This parameter can be useful for comparing MOS dosimeters.}, language = {en} } @phdthesis{Duchrau2024, author = {Duchrau, Georg}, title = {M{\"o}glichkeiten und Grenzen des erweiterten Cross Parity Codes}, school = {Universit{\"a}t Potsdam}, pages = {93}, year = {2024}, language = {de} } @phdthesis{Wang2011, author = {Wang, Long}, title = {X-tracking the usage interest on web sites}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-51077}, school = {Universit{\"a}t Potsdam}, year = {2011}, abstract = {The exponential expanding of the numbers of web sites and Internet users makes WWW the most important global information resource. From information publishing and electronic commerce to entertainment and social networking, the Web allows an inexpensive and efficient access to the services provided by individuals and institutions. The basic units for distributing these services are the web sites scattered throughout the world. However, the extreme fragility of web services and content, the high competence between similar services supplied by different sites, and the wide geographic distributions of the web users drive the urgent requirement from the web managers to track and understand the usage interest of their web customers. This thesis, "X-tracking the Usage Interest on Web Sites", aims to fulfill this requirement. "X" stands two meanings: one is that the usage interest differs from various web sites, and the other is that usage interest is depicted from multi aspects: internal and external, structural and conceptual, objective and subjective. "Tracking" shows that our concentration is on locating and measuring the differences and changes among usage patterns. This thesis presents the methodologies on discovering usage interest on three kinds of web sites: the public information portal site, e-learning site that provides kinds of streaming lectures and social site that supplies the public discussions on IT issues. On different sites, we concentrate on different issues related with mining usage interest. The educational information portal sites were the first implementation scenarios on discovering usage patterns and optimizing the organization of web services. In such cases, the usage patterns are modeled as frequent page sets, navigation paths, navigation structures or graphs. However, a necessary requirement is to rebuild the individual behaviors from usage history. We give a systematic study on how to rebuild individual behaviors. Besides, this thesis shows a new strategy on building content clusters based on pair browsing retrieved from usage logs. The difference between such clusters and the original web structure displays the distance between the destinations from usage side and the expectations from design side. Moreover, we study the problem on tracking the changes of usage patterns in their life cycles. The changes are described from internal side integrating conceptual and structure features, and from external side for the physical features; and described from local side measuring the difference between two time spans, and global side showing the change tendency along the life cycle. A platform, Web-Cares, is developed to discover the usage interest, to measure the difference between usage interest and site expectation and to track the changes of usage patterns. E-learning site provides the teaching materials such as slides, recorded lecture videos and exercise sheets. We focus on discovering the learning interest on streaming lectures, such as real medias, mp4 and flash clips. Compared to the information portal site, the usage on streaming lectures encapsulates the variables such as viewing time and actions during learning processes. The learning interest is discovered in the form of answering 6 questions, which covers finding the relations between pieces of lectures and the preference among different forms of lectures. We prefer on detecting the changes of learning interest on the same course from different semesters. The differences on the content and structure between two courses leverage the changes on the learning interest. We give an algorithm on measuring the difference on learning interest integrated with similarity comparison between courses. A search engine, TASK-Moniminer, is created to help the teacher query the learning interest on their streaming lectures on tele-TASK site. Social site acts as an online community attracting web users to discuss the common topics and share their interesting information. Compared to the public information portal site and e-learning web site, the rich interactions among users and web content bring the wider range of content quality, on the other hand, provide more possibilities to express and model usage interest. We propose a framework on finding and recommending high reputation articles in a social site. We observed that the reputation is classified into global and local categories; the quality of the articles having high reputation is related with the content features. Based on these observations, our framework is implemented firstly by finding the articles having global or local reputation, and secondly clustering articles based on their content relations, and then the articles are selected and recommended from each cluster based on their reputation ranks.}, language = {en} } @phdthesis{Schrape2023, author = {Schrape, Oliver}, title = {Methodology for standard cell-based design and implementation of reliable and robust hardware systems}, doi = {10.25932/publishup-58932}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-589326}, school = {Universit{\"a}t Potsdam}, pages = {xi, 181}, year = {2023}, abstract = {Reliable and robust data processing is one of the hardest requirements for systems in fields such as medicine, security, automotive, aviation, and space, to prevent critical system failures caused by changes in operating or environmental conditions. In particular, Signal Integrity (SI) effects such as crosstalk may distort the signal information in sensitive mixed-signal designs. A challenge for hardware systems used in the space are radiation effects. Namely, Single Event Effects (SEEs) induced by high-energy particle hits may lead to faulty computation, corrupted configuration settings, undesired system behavior, or even total malfunction. Since these applications require an extra effort in design and implementation, it is beneficial to master the standard cell design process and corresponding design flow methodologies optimized for such challenges. Especially for reliable, low-noise differential signaling logic such as Current Mode Logic (CML), a digital design flow is an orthogonal approach compared to traditional manual design. As a consequence, mandatory preliminary considerations need to be addressed in more detail. First of all, standard cell library concepts with suitable cell extensions for reliable systems and robust space applications have to be elaborated. Resulting design concepts at the cell level should enable the logical synthesis for differential logic design or improve the radiation-hardness. In parallel, the main objectives of the proposed cell architectures are to reduce the occupied area, power, and delay overhead. Second, a special setup for standard cell characterization is additionally required for a proper and accurate logic gate modeling. Last but not least, design methodologies for mandatory design flow stages such as logic synthesis and place and route need to be developed for the respective hardware systems to keep the reliability or the radiation-hardness at an acceptable level. This Thesis proposes and investigates standard cell-based design methodologies and techniques for reliable and robust hardware systems implemented in a conventional semi-conductor technology. The focus of this work is on reliable differential logic design and robust radiation-hardening-by-design circuits. The synergistic connections of the digital design flow stages are systematically addressed for these two types of hardware systems. In more detail, a library for differential logic is extended with single-ended pseudo-gates for intermediate design steps to support the logic synthesis and layout generation with commercial Computer-Aided Design (CAD) tools. Special cell layouts are proposed to relax signal routing. A library set for space applications is similarly extended by novel Radiation-Hardening-by-Design (RHBD) Triple Modular Redundancy (TMR) cells, enabling a one fault correction. Therein, additional optimized architectures for glitch filter cells, robust scannable and self-correcting flip-flops, and clock-gates are proposed. The circuit concepts and the physical layout representation views of the differential logic gates and the RHBD cells are discussed. However, the quality of results of designs depends implicitly on the accuracy of the standard cell characterization which is examined for both types therefore. The entire design flow is elaborated from the hardware design description to the layout representations. A 2-Phase routing approach together with an intermediate design conversion step is proposed after the initial place and route stage for reliable, pure differential designs, whereas a special constraining for RHBD applications in a standard technology is presented. The digital design flow for differential logic design is successfully demonstrated on a reliable differential bipolar CML application. A balanced routing result of its differential signal pairs is obtained by the proposed 2-Phase-routing approach. Moreover, the elaborated standard cell concepts and design methodology for RHBD circuits are applied to the digital part of a 7.5-15.5 MSPS 14-bit Analog-to-Digital Converter (ADC) and a complex microcontroller architecture. The ADC is implemented in an unhardened standard semiconductor technology and successfully verified by electrical measurements. The overhead of the proposed hardening approach is additionally evaluated by design exploration of the microcontroller application. Furthermore, the first obtained related measurement results of novel RHBD-∆TMR flip-flops show a radiation-tolerance up to a threshold Linear Energy Transfer (LET) of 46.1, 52.0, and 62.5 MeV cm2 mg-1 and savings in silicon area of 25-50 \% for selected TMR standard cell candidates. As a conclusion, the presented design concepts at the cell and library levels, as well as the design flow modifications are adaptable and transferable to other technology nodes. In particular, the design of hybrid solutions with integrated reliable differential logic modules together with robust radiation-tolerant circuit parts is enabled by the standard cell concepts and design methods proposed in this work.}, language = {en} } @article{HilscherBraunRichteretal.2009, author = {Hilscher, Martin and Braun, Michael and Richter, Michael and Leininger, Andreas and G{\"o}ssel, Michael}, title = {X-tolerant test data compaction with accelerated shift registers}, issn = {0923-8174}, doi = {10.1007/s10836-009-5107-5}, year = {2009}, abstract = {Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution.}, language = {en} } @article{GoesselSogomonyan1996, author = {G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {A new self-testing parity checker for ultra-reliable applications}, year = {1996}, language = {en} } @phdthesis{Seuring2000, author = {Seuring, Markus}, title = {Output space compaction for testing and concurrent checking}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-0000165}, school = {Universit{\"a}t Potsdam}, year = {2000}, abstract = {In der Dissertation werden neue Entwurfsmethoden f{\"u}r Kompaktoren f{\"u}r die Ausg{\"a}nge von digitalen Schaltungen beschrieben, die die Anzahl der zu testenden Ausg{\"a}nge drastisch verkleinern und dabei die Testbarkeit der Schaltungen nur wenig oder gar nicht verschlechtern. Der erste Teil der Arbeit behandelt f{\"u}r kombinatorische Schaltungen Methoden, die die Struktur der Schaltungen beim Entwurf der Kompaktoren ber{\"u}cksichtigen. Verschiedene Algorithmen zur Analyse von Schaltungsstrukturen werden zum ersten Mal vorgestellt und untersucht. Die Komplexit{\"a}t der vorgestellten Verfahren zur Erzeugung von Kompaktoren ist linear bez{\"u}glich der Anzahl der Gatter in der Schaltung und ist damit auf sehr große Schaltungen anwendbar. Im zweiten Teil wird erstmals ein solches Verfahren f{\"u}r sequentielle Schaltkreise beschrieben. Dieses Verfahren baut im wesentlichen auf das erste auf. Der dritte Teil beschreibt eine Entwurfsmethode, die keine Informationen {\"u}ber die interne Struktur der Schaltung oder {\"u}ber das zugrundeliegende Fehlermodell ben{\"o}tigt. Der Entwurf basiert alleine auf einem vorgegebenen Satz von Testvektoren und die dazugeh{\"o}renden Testantworten der fehlerfreien Schaltung. Ein nach diesem Verfahren erzeugter Kompaktor maskiert keinen der Fehler, die durch das Testen mit den vorgegebenen Vektoren an den Ausg{\"a}ngen der Schaltung beobachtbar sind.}, language = {en} } @phdthesis{Chen2023, author = {Chen, Junchao}, title = {A self-adaptive resilient method for implementing and managing the high-reliability processing system}, doi = {10.25932/publishup-58313}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-583139}, school = {Universit{\"a}t Potsdam}, pages = {XXIII, 167}, year = {2023}, abstract = {As a result of CMOS scaling, radiation-induced Single-Event Effects (SEEs) in electronic circuits became a critical reliability issue for modern Integrated Circuits (ICs) operating under harsh radiation conditions. SEEs can be triggered in combinational or sequential logic by the impact of high-energy particles, leading to destructive or non-destructive faults, resulting in data corruption or even system failure. Typically, the SEE mitigation methods are deployed statically in processing architectures based on the worst-case radiation conditions, which is most of the time unnecessary and results in a resource overhead. Moreover, the space radiation conditions are dynamically changing, especially during Solar Particle Events (SPEs). The intensity of space radiation can differ over five orders of magnitude within a few hours or days, resulting in several orders of magnitude fault probability variation in ICs during SPEs. This thesis introduces a comprehensive approach for designing a self-adaptive fault resilient multiprocessing system to overcome the static mitigation overhead issue. This work mainly addresses the following topics: (1) Design of on-chip radiation particle monitor for real-time radiation environment detection, (2) Investigation of space environment predictor, as support for solar particle events forecast, (3) Dynamic mode configuration in the resilient multiprocessing system. Therefore, according to detected and predicted in-flight space radiation conditions, the target system can be configured to use no mitigation or low-overhead mitigation during non-critical periods of time. The redundant resources can be used to improve system performance or save power. On the other hand, during increased radiation activity periods, such as SPEs, the mitigation methods can be dynamically configured appropriately depending on the real-time space radiation environment, resulting in higher system reliability. Thus, a dynamic trade-off in the target system between reliability, performance and power consumption in real-time can be achieved. All results of this work are evaluated in a highly reliable quad-core multiprocessing system that allows the self-adaptive setting of optimal radiation mitigation mechanisms during run-time. Proposed methods can serve as a basis for establishing a comprehensive self-adaptive resilient system design process. Successful implementation of the proposed design in the quad-core multiprocessor shows its application perspective also in the other designs.}, language = {en} } @phdthesis{Nordmann2020, author = {Nordmann, Paul-Patrick}, title = {Fehlerkorrektur von Speicherfehlern mit Low-Density-Parity-Check-Codes}, doi = {10.25932/publishup-48048}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-480480}, school = {Universit{\"a}t Potsdam}, pages = {IV, 99, XII}, year = {2020}, abstract = {Die Fehlerkorrektur in der Codierungstheorie besch{\"a}ftigt sich mit der Erkennung und Behebung von Fehlern bei der {\"U}bertragung und auch Sicherung von Nachrichten. Hierbei wird die Nachricht durch zus{\"a}tzliche Informationen in ein Codewort kodiert. Diese Kodierungsverfahren besitzen verschiedene Anspr{\"u}che, wie zum Beispiel die maximale Anzahl der zu korrigierenden Fehler und die Geschwindigkeit der Korrektur. Ein g{\"a}ngiges Codierungsverfahren ist der BCH-Code, welches industriell f{\"u}r bis zu vier Fehler korrigiere Codes Verwendung findet. Ein Nachteil dieser Codes ist die technische Durchlaufzeit f{\"u}r die Berechnung der Fehlerstellen mit zunehmender Codel{\"a}nge. Die Dissertation stellt ein neues Codierungsverfahren vor, bei dem durch spezielle Anordnung kleinere Codel{\"a}ngen eines BCH-Codes ein langer Code erzeugt wird. Diese Anordnung geschieht {\"u}ber einen weiteren speziellen Code, einem LDPC-Code, welcher f{\"u}r eine schneller Fehlererkennung konzipiert ist. Hierf{\"u}r wird ein neues Konstruktionsverfahren vorgestellt, welches einen Code f{\"u}r einen beliebige L{\"a}nge mit vorgebbaren beliebigen Anzahl der zu korrigierenden Fehler vorgibt. Das vorgestellte Konstruktionsverfahren erzeugt zus{\"a}tzlich zum schnellen Verfahren der Fehlererkennung auch eine leicht und schnelle Ableitung eines Verfahrens zu Kodierung der Nachricht zum Codewort. Dies ist in der Literatur f{\"u}r die LDPC-Codes bis zum jetzigen Zeitpunkt einmalig. Durch die Konstruktion eines LDPC-Codes wird ein Verfahren vorgestellt wie dies mit einem BCH-Code kombiniert wird, wodurch eine Anordnung des BCH-Codes in Bl{\"o}cken erzeugt wird. Neben der allgemeinen Beschreibung dieses Codes, wird ein konkreter Code f{\"u}r eine 2-Bitfehlerkorrektur beschrieben. Diese besteht aus zwei Teilen, welche in verschiedene Varianten beschrieben und verglichen werden. F{\"u}r bestimmte L{\"a}ngen des BCH-Codes wird ein Problem bei der Korrektur aufgezeigt, welche einer algebraischen Regel folgt. Der BCH-Code wird sehr allgemein beschrieben, doch existiert durch bestimmte Voraussetzungen ein BCH-Code im engerem Sinne, welcher den Standard vorgibt. Dieser BCH-Code im engerem Sinne wird in dieser Dissertation modifiziert, so dass das algebraische Problem bei der 2-Bitfehler Korrektur bei der Kombination mit dem LDPC-Code nicht mehr existiert. Es wird gezeigt, dass nach der Modifikation der neue Code weiterhin ein BCH-Code im allgemeinen Sinne ist, welcher 2-Bitfehler korrigieren und 3-Bitfehler erkennen kann. Bei der technischen Umsetzung der Fehlerkorrektur wird des Weiteren gezeigt, dass die Durchlaufzeiten des modifizierten Codes im Vergleich zum BCH-Code schneller ist und weiteres Potential f{\"u}r Verbesserungen besitzt. Im letzten Kapitel wird gezeigt, dass sich dieser modifizierte Code mit beliebiger L{\"a}nge eignet f{\"u}r die Kombination mit dem LDPC-Code, wodurch dieses Verfahren nicht nur umf{\"a}nglicher in der L{\"a}nge zu nutzen ist, sondern auch durch die schnellere Dekodierung auch weitere Vorteile gegen{\"u}ber einem BCH-Code im engerem Sinne besitzt.}, language = {de} } @phdthesis{Morozov2005, author = {Morozov, Alexei}, title = {Optimierung von Fehlererkennungsschaltungen auf der Grundlage von komplement{\"a}ren Erg{\"a}nzungen f{\"u}r 1-aus-3 und Berger Codes}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-5360}, school = {Universit{\"a}t Potsdam}, year = {2005}, abstract = {Die Dissertation stellt eine neue Herangehensweise an die L{\"o}sung der Aufgabe der funktionalen Diagnostik digitaler Systeme vor. In dieser Arbeit wird eine neue Methode f{\"u}r die Fehlererkennung vorgeschlagen, basierend auf der Logischen Erg{\"a}nzung und der Verwendung von Berger-Codes und dem 1-aus-3 Code. Die neue Fehlererkennungsmethode der Logischen Erg{\"a}nzung gestattet einen hohen Optimierungsgrad der ben{\"o}tigten Realisationsfl{\"a}che der konstruierten Fehlererkennungsschaltungen. Außerdem ist eins der wichtigen in dieser Dissertation gel{\"o}sten Probleme die Synthese vollst{\"a}ndig selbstpr{\"u}fender Schaltungen.}, subject = {logische Erg{\"a}nzung}, language = {de} } @article{GerberGoessel1994, author = {Gerber, Stefan and G{\"o}ssel, Michael}, title = {Detection of permanent faults of a floating point adder by pseudoduplication}, year = {1994}, language = {en} } @article{BhattacharyaDimitrievGoessel2000, author = {Bhattacharya, M. K. and Dimitriev, Alexej and G{\"o}ssel, Michael}, title = {Zero-aliasing space compresion using a single periodic output and its application to testing of embedded}, year = {2000}, language = {en} } @article{DimitrievSaposhnikovSaposhnikovetal.1999, author = {Dimitriev, Alexej and Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael}, title = {Concurrent checking of sequential circuits by alternating inputs}, year = {1999}, language = {en} } @article{KuentzerKrstić2020, author = {Kuentzer, Felipe A. and Krstić, Miloš}, title = {Soft error detection and correction architecture for asynchronous bundled data designs}, series = {IEEE transactions on circuits and systems}, volume = {67}, journal = {IEEE transactions on circuits and systems}, number = {12}, publisher = {Institute of Electrical and Electronics Engineers}, address = {New York}, issn = {1549-8328}, doi = {10.1109/TCSI.2020.2998911}, pages = {4883 -- 4894}, year = {2020}, abstract = {In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6\% to 17.6\%, and increasing energy efficiency, which can be up to 6.5\%.}, language = {en} } @article{SaposhnikovOtscheretnijSaposhnikovetal.1998, author = {Saposhnikov, Vl. V. and Otscheretnij, Vitalij and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Design of Fault-Tolerant Circuits by self-dual Duplication}, year = {1998}, language = {en} } @article{MoschaninSaposhnikovSaposhnikovetal.1996, author = {Moschanin, Wladimir and Saposhnikov, Vl. V. and Saposhnikov, Va. V. and G{\"o}ssel, Michael}, title = {Synthesis of self-dual multi-output combinational circuits for on-line Teting}, year = {1996}, language = {en} } @article{SeuringGoesselSogomonyan1998, author = {Seuring, Markus and G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {Ein strukturelles Verfahren zur Kompaktierung von Schaltungsausgaben f{\"u}r online-Fehlererkennungen und Selbstests}, year = {1998}, language = {de} } @article{SogomonyanGoessel1996, author = {Sogomonyan, Egor S. and G{\"o}ssel, Michael}, title = {Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems}, year = {1996}, language = {en} } @article{MorosovGoesselHartje1999, author = {Morosov, Andrej and G{\"o}ssel, Michael and Hartje, Hendrik}, title = {Reduced area overhead of the input party for code-disjoint circuits}, year = {1999}, language = {en} } @article{SeuringGoessel1999, author = {Seuring, Markus and G{\"o}ssel, Michael}, title = {A structural method for output compaction of sequential automata implemented as circuits}, year = {1999}, language = {en} } @book{SeuringGoessel1998, author = {Seuring, Markus and G{\"o}ssel, Michael}, title = {A structural approach for space compaction for sequential circuits}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, volume = {1998, 05}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, publisher = {Univ.}, address = {Potsdam}, issn = {0946-7580}, pages = {16 Bl. : graph. Darst.}, year = {1998}, language = {en} } @article{HlawiczkaGoesselSogomonyan1997, author = {Hlawiczka, A. and G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {A linear code-preserving signature analyzer COPMISR}, isbn = {0-8186-7810-0}, year = {1997}, language = {en} } @article{BogueGoesselJuergensenetal.1998, author = {Bogue, Ted and G{\"o}ssel, Michael and J{\"u}rgensen, Helmut and Zorian, Yervant}, title = {Built-in self-Test with an alternating output}, isbn = {0-8186-8359-7}, year = {1998}, language = {en} } @article{OtscheretnijGoesselSaposhnikovetal.1998, author = {Otscheretnij, Vitalij and G{\"o}ssel, Michael and Saposhnikov, Vl. V. and Saposhnikov, V. V.}, title = {Fault-tolerant self-dual circuits with error detection by parity- and group parity prediction}, year = {1998}, language = {en} }