@article{AndjelkovicSimevskiChenetal.2022,
  author    = {Andjelkovic, Marko and Simevski, Aleksandar and Chen, Junchao and Schrape, Oliver and Stamenkovic, Zoran and Krstić, Miloš and Ilic, Stefan and Ristic, Goran and Jaksic, Aleksandar and Vasovic, Nikola and Duane, Russell and Palma, Alberto J. and Lallena, Antonio M. and Carvajal, Miguel A.},
  title     = {A design concept for radiation hardened RADFET readout system for space applications},
  series = {Microprocessors and microsystems},
  volume    = {90},
  journal   = {Microprocessors and microsystems},
  publisher = {Elsevier},
  address   = {Amsterdam},
  issn      = {0141-9331},
  doi       = {10.1016/j.micpro.2022.104486},
  pages     = {18},
  year      = {2022},
  abstract  = {Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET's response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions.},
  language  = {en}
}
@article{DelgrandeSchaubTompits2003,
  author    = {Delgrande, James Patrick and Schaub, Torsten H. and Tompits, Hans},
  title     = {A framework for compiling preferences in logic programs},
  year      = {2003},
  language  = {en}
}
@article{KreowskyStabernack2021,
  author    = {Kreowsky, Philipp and Stabernack, Christian Benno},
  title     = {A full-featured FPGA-based pipelined architecture for SIFT extraction},
  series = {IEEE access : practical research, open solutions / Institute of Electrical and Electronics Engineers},
  volume    = {9},
  journal   = {IEEE access : practical research, open solutions / Institute of Electrical and Electronics Engineers},
  publisher = {Inst. of Electr. and Electronics Engineers},
  address   = {New York, NY},
  issn      = {2169-3536},
  doi       = {10.1109/ACCESS.2021.3104387},
  pages     = {128564 -- 128573},
  year      = {2021},
  abstract  = {Image feature detection is a key task in computer vision. Scale Invariant Feature Transform (SIFT) is a prevalent and well known algorithm for robust feature detection. However, it is computationally demanding and software implementations are not applicable for real-time performance. In this paper, a versatile and pipelined hardware implementation is proposed, that is capable of computing keypoints and rotation invariant descriptors on-chip. All computations are performed in single precision floating-point format which makes it possible to implement the original algorithm with little alteration. Various rotation resolutions and filter kernel sizes are supported for images of any resolution up to ultra-high definition. For full high definition images, 84 fps can be processed. Ultra high definition images can be processed at 21 fps.},
  language  = {en}
}
@article{DelgrandeSchaubTompits2007,
  author    = {Delgrande, James Patrick and Schaub, Torsten H. and Tompits, Hans},
  title     = {A general framework for expressing preferences in causal reasoning and planning},
  issn      = {0955-792X},
  doi       = {10.1093/logcom/exm046},
  year      = {2007},
  abstract  = {We consider the problem of representing arbitrary preferences in causal reasoning and planning systems. In planning, a preference may be seen as a goal or constraint that is desirable, but not necessary, to satisfy. To begin, we define a very general query language for histories, or interleaved sequences of world states and actions. Based on this, we specify a second language in which preferences are defined. A single preference defines a binary relation on histories, indicating that one history is preferred to the other. From this, one can define global preference orderings on the set of histories, the maximal elements of which are the preferred histories. The approach is very general and flexible; thus it constitutes a base language in terms of which higher-level preferences may be defined. To this end, we investigate two fundamental types of preferences that we call choice and temporal preferences. We consider concrete strategies for these types of preferences and encode them in terms of our framework. We suggest how to express aggregates in the approach, allowing, e.g. the expression of a preference for histories with lowest total action costs. Last, our approach can be used to express other approaches and so serves as a common framework in which such approaches can be expressed and compared. We illustrate this by indicating how an approach due to Son and Pontelli can be encoded in our approach, as well as the language PDDL3.},
  language  = {en}
}
@article{DelgrandeSchaubTompits2001,
  author    = {Delgrande, James Patrick and Schaub, Torsten H. and Tompits, Hans},
  title     = {A generic compiler for ordered logic programs},
  isbn      = {3-540-42593-4},
  year      = {2001},
  language  = {en}
}
@article{AngerKonczakLinkeetal.2005,
  author    = {Anger, Christian and Konczak, Kathrin and Linke, Thomas and Schaub, Torsten H.},
  title     = {A Glimpse of Answer Set Programming},
  issn      = {0170-4516},
  year      = {2005},
  language  = {en}
}
@incollection{KiyGessnerLuckeetal.2015,
  author    = {Kiy, Alexander and Geßner, Hendrik and Lucke, Ulrike and Gr{\"u}newald, Franka},
  title     = {A Hybrid and Modular Framework for Mobile Campus Applications},
  series = {i-com},
  volume    = {2015},
  booktitle = {i-com},
  number    = {14},
  publisher = {de Gruyter},
  address   = {Berlin},
  issn      = {2196-6826},
  doi       = {10.1515/icom-2015-0016},
  publisher      = {Universit{\"a}t Potsdam},
  pages     = {63 -- 73},
  year      = {2015},
  abstract  = {Mobile devices and associated applications (apps) are an indispensable part of daily life and provide access to important information anytime and anywhere. However, the availability of university-wide services in the mobile sector is still poor. If they exist they usually result from individual activities of students and teachers. Mobile applications can have an essential impact on the improvement of students' self-organization as well as on the design and enhancement of specific learning scenarios, though. This article introduces a mobile campus app framework, which integrates central campus services and decentralized learning applications. An analysis of strengths and weaknesses of different approaches is presented to summarize and evaluate them in terms of requirements, development, maintenance and operation. The article discusses the underlying service-oriented architecture that allows transferring the campus app to other universities or institutions at reasonable cost. It concludes with a presentation of the results as well as ongoing discussions and future work},
  language  = {en}
}
@article{TiwariPrakashGrossetal.2020,
  author    = {Tiwari, Abhishek and Prakash, Jyoti and Groß, Sascha and Hammer, Christian},
  title     = {A large scale analysis of Android},
  series = {The journal of systems and software},
  volume    = {170},
  journal   = {The journal of systems and software},
  publisher = {Elsevier},
  address   = {New York},
  issn      = {0164-1212},
  doi       = {10.1016/j.jss.2020.110775},
  pages     = {17},
  year      = {2020},
  abstract  = {Many Android applications embed webpages via WebView components and execute JavaScript code within Android. Hybrid applications leverage dedicated APIs to load a resource and render it in a WebView. Furthermore, Android objects can be shared with the JavaScript world. However, bridging the interfaces of the Android and JavaScript world might also incur severe security threats: Potentially untrusted webpages and their JavaScript might interfere with the Android environment and its access to native features. No general analysis is currently available to assess the implications of such hybrid apps bridging the two worlds. To understand the semantics and effects of hybrid apps, we perform a large-scale study on the usage of the hybridization APIs in the wild. We analyze and categorize the parameters to hybridization APIs for 7,500 randomly selected and the 196 most popular applications from the Google Playstore as well as 1000 malware samples. Our results advance the general understanding of hybrid applications, as well as implications for potential program analyses, and the current security situation: We discovered thousands of flows of sensitive data from Android to JavaScript, the vast majority of which could flow to potentially untrustworthy code. Our analysis identified numerous web pages embedding vulnerabilities, which we exemplarily exploited. Additionally, we discovered a multitude of applications in which potentially untrusted JavaScript code may interfere with (trusted) Android objects, both in benign and malign applications.},
  language  = {en}
}
@article{HlawiczkaGoesselSogomonyan1997,
  author    = {Hlawiczka, A. and G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {A linear code-preserving signature analyzer COPMISR},
  isbn      = {0-8186-7810-0},
  year      = {1997},
  language  = {en}
}
@unpublished{Arnold2009,
  author    = {Arnold, Holger},
  title     = {A linearized DPLL calculus with clause learning (2nd, revised version)},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-29080},
  year      = {2009},
  abstract  = {Many formal descriptions of DPLL-based SAT algorithms either do not include all essential proof techniques applied by modern SAT solvers or are bound to particular heuristics or data structures. This makes it difficult to analyze proof-theoretic properties or the search complexity of these algorithms. In this paper we try to improve this situation by developing a nondeterministic proof calculus that models the functioning of SAT algorithms based on the DPLL calculus with clause learning. This calculus is independent of implementation details yet precise enough to enable a formal analysis of realistic DPLL-based SAT algorithms.},
  language  = {en}
}
@article{Arnold2007,
  author    = {Arnold, Holger},
  title     = {A linearized DPLL calculus with learning},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-15421},
  year      = {2007},
  abstract  = {This paper describes the proof calculus LD for clausal propositional logic, which is a linearized form of the well-known DPLL calculus extended by clause learning. It is motivated by the demand to model how current SAT solvers built on clause learning are working, while abstracting from decision heuristics and implementation details. The calculus is proved sound and terminating. Further, it is shown that both the original DPLL calculus and the conflict-directed backtracking calculus with clause learning, as it is implemented in many current SAT solvers, are complete and proof-confluent instances of the LD calculus.},
  language  = {en}
}
@phdthesis{Scherfenberg2012,
  author    = {Scherfenberg, Ivonne},
  title     = {A logic-based Framwork to enable Attribute Assurance for Digital Identities in Service-oriented Architectures and the Web},
  address   = {Potsdam},
  pages     = {126 S.},
  year      = {2012},
  language  = {en}
}
@article{BesnardHunter2001,
  author    = {Besnard, Philippe and Hunter, Anthony},
  title     = {A logic-based theory of deductive arguments},
  issn      = {0004-3702},
  year      = {2001},
  language  = {en}
}
@article{SaposhnikovSaposhnikovGoesseletal.1999,
  author    = {Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael and Morosov, Andrej},
  title     = {A method of construction of combinational self-checking units with detection of all single faults},
  year      = {1999},
  language  = {en}
}
@phdthesis{Andjelkovic2021,
  author    = {Andjelkovic, Marko},
  title     = {A methodology for characterization, modeling and mitigation of single event transient effects in CMOS standard combinational cells},
  doi       = {10.25932/publishup-53484},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-534843},
  school      = {Universit{\"a}t Potsdam},
  pages     = {xxiv, 216},
  year      = {2021},
  abstract  = {With the downscaling of CMOS technologies, the radiation-induced Single Event Transient (SET) effects in combinational logic have become a critical reliability issue for modern integrated circuits (ICs) intended for operation under harsh radiation conditions. The SET pulses generated in combinational logic may propagate through the circuit and eventually result in soft errors. It has thus become an imperative to address the SET effects in the early phases of the radiation-hard IC design. In general, the soft error mitigation solutions should accommodate both static and dynamic measures to ensure the optimal utilization of available resources. An efficient soft-error-aware design should address synergistically three main aspects: (i) characterization and modeling of soft errors, (ii) multi-level soft error mitigation, and (iii) online soft error monitoring. Although significant results have been achieved, the effectiveness of SET characterization methods, accuracy of predictive SET models, and efficiency of SET mitigation measures are still critical issues. Therefore, this work addresses the following topics: (i) Characterization and modeling of SET effects in standard combinational cells, (ii) Static mitigation of SET effects in standard combinational cells, and (iii) Online particle detection, as a support for dynamic soft error mitigation. Since the standard digital libraries are widely used in the design of radiation-hard ICs, the characterization of SET effects in standard cells and the availability of accurate SET models for the Soft Error Rate (SER) evaluation are the main prerequisites for efficient radiation-hard design. This work introduces an approach for the SPICE-based standard cell characterization with the reduced number of simulations, improved SET models and optimized SET sensitivity database. It has been shown that the inherent similarities in the SET response of logic cells for different input levels can be utilized to reduce the number of required simulations. Based on characterization results, the fitting models for the SET sensitivity metrics (critical charge, generated SET pulse width and propagated SET pulse width) have been developed. The proposed models are based on the principle of superposition, and they express explicitly the dependence of the SET sensitivity of individual combinational cells on design, operating and irradiation parameters. In contrast to the state-of-the-art characterization methodologies which employ extensive look-up tables (LUTs) for storing the simulation results, this work proposes the use of LUTs for storing the fitting coefficients of the SET sensitivity models derived from the characterization results. In that way the amount of characterization data in the SET sensitivity database is reduced significantly. The initial step in enhancing the robustness of combinational logic is the application of gate-level mitigation techniques. As a result, significant improvement of the overall SER can be achieved with minimum area, delay and power overheads. For the SET mitigation in standard cells, it is essential to employ the techniques that do not require modifying the cell structure. This work introduces the use of decoupling cells for improving the robustness of standard combinational cells. By insertion of two decoupling cells at the output of a target cell, the critical charge of the cell's output node is increased and the attenuation of short SETs is enhanced. In comparison to the most common gate-level techniques (gate upsizing and gate duplication), the proposed approach provides better SET filtering. However, as there is no single gate-level mitigation technique with optimal performance, a combination of multiple techniques is required. This work introduces a comprehensive characterization of gate-level mitigation techniques aimed to quantify their impact on the SET robustness improvement, as well as introduced area, delay and power overhead per gate. By characterizing the gate-level mitigation techniques together with the standard cells, the required effort in subsequent SER analysis of a target design can be reduced. The characterization database of the hardened standard cells can be utilized as a guideline for selection of the most appropriate mitigation solution for a given design. As a support for dynamic soft error mitigation techniques, it is important to enable the online detection of energetic particles causing the soft errors. This allows activating the power-greedy fault-tolerant configurations based on N-modular redundancy only at the high radiation levels. To enable such a functionality, it is necessary to monitor both the particle flux and the variation of particle LET, as these two parameters contribute significantly to the system SER. In this work, a particle detection approach based on custom-sized pulse stretching inverters is proposed. Employing the pulse stretching inverters connected in parallel enables to measure the particle flux in terms of the number of detected SETs, while the particle LET variations can be estimated from the distribution of SET pulse widths. This approach requires a purely digital processing logic, in contrast to the standard detectors which require complex mixed-signal processing. Besides the possibility of LET monitoring, additional advantages of the proposed particle detector are low detection latency and power consumption, and immunity to error accumulation. The results achieved in this thesis can serve as a basis for establishment of an overall soft-error-aware database for a given digital library, and a comprehensive multi-level radiation-hard design flow that can be implemented with the standard IC design tools. The following step will be to evaluate the achieved results with the irradiation experiments.},
  language  = {en}
}
@phdthesis{Wolter2010,
  author    = {Wolter, Christian},
  title     = {A methodology for model-driven process security},
  address   = {Potsdam},
  pages     = {xv, 144 S. : graph. Darst.},
  year      = {2010},
  language  = {en}
}
@article{BrueningSchaub1996,
  author    = {Br{\"u}ning, Stefan and Schaub, Torsten H.},
  title     = {A model-based approach to consistency-checking},
  isbn      = {3-540-61286-6},
  year      = {1996},
  language  = {en}
}
@article{DelgrandeSchaubTompitsetal.2013,
  author    = {Delgrande, James and Schaub, Torsten H. and Tompits, Hans and Woltran, Stefan},
  title     = {A model-theoretic approach to belief change in answer set programming},
  series = {ACM transactions on computational logic},
  volume    = {14},
  journal   = {ACM transactions on computational logic},
  number    = {2},
  publisher = {Association for Computing Machinery},
  address   = {New York},
  issn      = {1529-3785},
  doi       = {10.1145/2480759.2480766},
  pages     = {46},
  year      = {2013},
  abstract  = {We address the problem of belief change in (nonmonotonic) logic programming under answer set semantics. Our formal techniques are analogous to those of distance-based belief revision in propositional logic. In particular, we build upon the model theory of logic programs furnished by SE interpretations, where an SE interpretation is a model of a logic program in the same way that a classical interpretation is a model of a propositional formula. Hence we extend techniques from the area of belief revision based on distance between models to belief change in logic programs. We first consider belief revision: for logic programs P and Q, the goal is to determine a program R that corresponds to the revision of P by Q, denoted P * Q. We investigate several operators, including (logic program) expansion and two revision operators based on the distance between the SE models of logic programs. It proves to be the case that expansion is an interesting operator in its own right, unlike in classical belief revision where it is relatively uninteresting. Expansion and revision are shown to satisfy a suite of interesting properties; in particular, our revision operators satisfy all or nearly all of the AGM postulates for revision. We next consider approaches for merging a set of logic programs, P-1,...,P-n. Again, our formal techniques are based on notions of relative distance between the SE models of the logic programs. Two approaches are examined. The first informally selects for each program P-i those models of P-i that vary the least from models of the other programs. The second approach informally selects those models of a program P-0 that are closest to the models of programs P-1,...,P-n. In this case, P-0 can be thought of as a set of database integrity constraints. We examine these operators with regards to how they satisfy relevant postulate sets. Last, we present encodings for computing the revision as well as the merging of logic programs within the same logic programming framework. This gives rise to a direct implementation of our approach in terms of off-the-shelf answer set solvers. These encodings also reflect the fact that our change operators do not increase the complexity of the base formalism.},
  language  = {en}
}
@article{SogomonyanSinghGoessel1999,
  author    = {Sogomonyan, Egor S. and Singh, Adit D. and G{\"o}ssel, Michael},
  title     = {A multi-mode scannable memory element for high test application efficiency and delay testing},
  year      = {1999},
  language  = {en}
}
@article{SogomonyanSinghGoessel1998,
  author    = {Sogomonyan, Egor S. and Singh, Adit D. and G{\"o}ssel, Michael},
  title     = {A multi-mode scannable memory element for high test application efficiency and delay testing},
  year      = {1998},
  language  = {en}
}
@phdthesis{Ghasemzadeh2005,
  author    = {Ghasemzadeh, Mohammad},
  title     = {A new algorithm for the quantified satisfiability problem, based on zero-suppressed binary decision diagrams and memoization},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-6378},
  school      = {Universit{\"a}t Potsdam},
  year      = {2005},
  abstract  = {Quantified Boolean formulas (QBFs) play an important role in theoretical computer science. QBF extends propositional logic in such a way that many advanced forms of reasoning can be easily formulated and evaluated. In this dissertation we present our ZQSAT, which is an algorithm for evaluating quantified Boolean formulas. ZQSAT is based on ZBDD: Zero-Suppressed Binary Decision Diagram , which is a variant of BDD, and an adopted version of the DPLL algorithm. It has been implemented in C using the CUDD: Colorado University Decision Diagram package. The capability of ZBDDs in storing sets of subsets efficiently enabled us to store the clauses of a QBF very compactly and let us to embed the notion of memoization to the DPLL algorithm. These points led us to implement the search algorithm in such a way that we could store and reuse the results of all previously solved subformulas with a little overheads. ZQSAT can solve some sets of standard QBF benchmark problems (known to be hard for DPLL based algorithms) faster than the best existing solvers. In addition to prenex-CNF, ZQSAT accepts prenex-NNF formulas. We show and prove how this capability can be exponentially beneficial.},
  subject      = {Bin{\"a}res Entscheidungsdiagramm},
  language  = {en}
}
@article{Gohlke1995,
  author    = {Gohlke, Mario},
  title     = {A new approach for model-based recognition using colour regions},
  year      = {1995},
  language  = {en}
}
@article{SaposhnikovMorosovSaposhnikovetal.1998,
  author    = {Saposhnikov, V. V. and Morosov, Andrej and Saposhnikov, Vl. V. and G{\"o}ssel, Michael},
  title     = {A new design method for self-checking unidirectional combinational circuits},
  year      = {1998},
  language  = {en}
}
@article{Richter1995,
  author    = {Richter, Peter},
  title     = {A new deterministic approach for the optimization of cable layouts for power supply systems},
  year      = {1995},
  language  = {en}
}
@article{Goessel1999,
  author    = {G{\"o}ssel, Michael},
  title     = {A new method of redundancy addition for circuit optimization},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {1999, 08},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ.},
  address   = {Potsdam},
  issn      = {0946-7580},
  pages     = {9 Bl.},
  year      = {1999},
  language  = {en}
}
@article{SogomonyanGoessel1995,
  author    = {Sogomonyan, Egor S. and G{\"o}ssel, Michael},
  title     = {A new parity preserving multi-input signature analyser},
  year      = {1995},
  language  = {en}
}
@book{SogomonyanMarienfeldOcheretnijetal.2003,
  author    = {Sogomonyan, Egor S. and Marienfeld, Daniel and Ocheretnij, V. and G{\"o}ssel, Michael},
  title     = {A new self-checking sum-bit duplicated carry-select adder},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {2003, 5},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ.},
  address   = {Potsdam},
  issn      = {0946-7580},
  pages     = {10 S.},
  year      = {2003},
  language  = {en}
}
@article{GoesselSogomonyan1996,
  author    = {G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {A new self-testing parity checker for ultra-reliable applications},
  year      = {1996},
  language  = {en}
}
@article{GoesselSogomonyanMorosov1999,
  author    = {G{\"o}ssel, Michael and Sogomonyan, Egor S. and Morosov, Andrej},
  title     = {A new totally error propagating compactor for arbitrary cores with digital interfaces},
  year      = {1999},
  language  = {en}
}
@article{KawanabeBlanchardSugiyamaetal.2006,
  author    = {Kawanabe, Motoaki and Blanchard, Gilles and Sugiyama, Masashi and Spokoiny, Vladimir G. and M{\"u}ller, Klaus-Robert},
  title     = {A novel dimension reduction procedure for searching non-Gaussian subspaces},
  issn      = {0302-9743},
  doi       = {10.1007/11679363_19},
  year      = {2006},
  abstract  = {In this article, we consider high-dimensional data which contains a low-dimensional non-Gaussian structure contaminated with Gaussian noise and propose a new linear method to identify the non-Gaussian subspace. Our method NGCA (Non-Gaussian Component Analysis) is based on a very general semi-parametric framework and has a theoretical guarantee that the estimation error of finding the non-Gaussian components tends to zero at a parametric rate. NGCA can be used not only as preprocessing for ICA, but also for extracting and visualizing more general structures like clusters. A numerical study demonstrates the usefulness of our method},
  language  = {en}
}
@article{LiangLiuLiuetal.2015,
  author    = {Liang, Feng and Liu, Yunzhen and Liu, Hai and Ma, Shilong and Schnor, Bettina},
  title     = {A Parallel Job Execution Time Estimation Approach Based on User Submission Patterns within Computational Grids},
  series = {International journal of parallel programming},
  volume    = {43},
  journal   = {International journal of parallel programming},
  number    = {3},
  publisher = {Springer},
  address   = {New York},
  issn      = {0885-7458},
  doi       = {10.1007/s10766-013-0294-1},
  pages     = {440 -- 454},
  year      = {2015},
  abstract  = {Scheduling performance in computational grid can potentially benefit a lot from accurate execution time estimation for parallel jobs. Most existing approaches for the parallel job execution time estimation, however, require ample past job traces and the explicit correlations between the job execution time and the outer layout parameters such as the consumed processor numbers, the user-estimated execution time and the job ID, which are hard to obtain or reveal. This paper presents and evaluates a novel execution time estimation approach for parallel jobs, the user-behavior clustering for execution time estimation, which can give more accurate execution time estimation for parallel jobs through exploring the job similarity and revealing the user submission patterns. Experiment results show that compared to the state-of-art algorithms, our approach can improve the accuracy of the job execution time estimation up to 5.6 \%, meanwhile the time that our approach spends on calculation can be reduced up to 3.8 \%.},
  language  = {en}
}
@article{GoesselSogomonyan1996,
  author    = {G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {A parity-preserving multi-input signature analyzer and it application for concurrent checking and BIST},
  year      = {1996},
  language  = {en}
}
@article{PearceSarsakovSchaubetal.2002,
  author    = {Pearce, David and Sarsakov, Vladimir and Schaub, Torsten H. and Tompits, Hans and Woltran, Stefan},
  title     = {A polynomial translation of logic programs with nested expressions into disjunctive logic programs},
  isbn      = {3-540-43930-7},
  year      = {2002},
  language  = {en}
}
@article{PearceSarsakovSchaubetal.2002,
  author    = {Pearce, David and Sarsakov, Vladimir and Schaub, Torsten H. and Tompits, Hans and Woltran, Stefan},
  title     = {A polynomial translation of logic programs with nested expressions into disjunctive logic programs : preliminary report},
  year      = {2002},
  language  = {en}
}
@article{DelgrandeSchaubTompits2007,
  author    = {Delgrande, James Patrick and Schaub, Torsten H. and Tompits, Hans},
  title     = {A preference-based framework for updating logic programs},
  isbn      = {978-3-540- 72199-4},
  year      = {2007},
  language  = {en}
}
@article{DelgrandeSchaubTompits2006,
  author    = {Delgrande, James Patrick and Schaub, Torsten H. and Tompits, Hans},
  title     = {A Preference-Based Framework for Updating logic Programs : preliminary reports},
  year      = {2006},
  language  = {en}
}
@book{PolyvyanyyKuropka2007,
  author    = {Polyvyanyy, Artem and Kuropka, Dominik},
  title     = {A Quantitative Evalution of the Enhanced Topic-based Vector Space Model},
  series = {Technische Berichte des Hasso-Plattner-Instituts f{\"u}r Softwaresystemtechnik an der Universit{\"a}t Potsda},
  volume    = {19},
  journal   = {Technische Berichte des Hasso-Plattner-Instituts f{\"u}r Softwaresystemtechnik an der Universit{\"a}t Potsda},
  publisher = {Universit{\"a}tsverlag Potsdam},
  address   = {Potsdam},
  isbn      = {978-3-939469-95-7},
  issn      = {1613-5652},
  pages     = {88 S.},
  year      = {2007},
  language  = {en}
}
@phdthesis{Mueller2012,
  author    = {M{\"u}ller, J{\"u}rgen J.},
  title     = {A real-time in-memory discovery service},
  address   = {Potsdam},
  pages     = {XXV, 172 S.},
  year      = {2012},
  language  = {en}
}
@article{Boerner1998,
  author    = {B{\"o}rner, Ferdinand},
  title     = {A remark on the finite lattice representation problem},
  year      = {1998},
  language  = {en}
}
@article{Schoebel2010,
  author    = {Sch{\"o}bel, Michael},
  title     = {A runtime environment for online processing of operating system kernel events},
  isbn      = {978-3-86956-036-6},
  year      = {2010},
  language  = {en}
}
@article{SogomonyanSinghGoessel1998,
  author    = {Sogomonyan, Egor S. and Singh, Adit D. and G{\"o}ssel, Michael},
  title     = {A scan based concrrent BIST approach for low cost on-line testing},
  year      = {1998},
  language  = {en}
}
@phdthesis{Chen2023,
  author    = {Chen, Junchao},
  title     = {A self-adaptive resilient method for implementing and managing the high-reliability processing system},
  doi       = {10.25932/publishup-58313},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus4-583139},
  school      = {Universit{\"a}t Potsdam},
  pages     = {XXIII, 167},
  year      = {2023},
  abstract  = {As a result of CMOS scaling, radiation-induced Single-Event Effects (SEEs) in electronic circuits became a critical reliability issue for modern Integrated Circuits (ICs) operating under harsh radiation conditions. SEEs can be triggered in combinational or sequential logic by the impact of high-energy particles, leading to destructive or non-destructive faults, resulting in data corruption or even system failure. Typically, the SEE mitigation methods are deployed statically in processing architectures based on the worst-case radiation conditions, which is most of the time unnecessary and results in a resource overhead. Moreover, the space radiation conditions are dynamically changing, especially during Solar Particle Events (SPEs). The intensity of space radiation can differ over five orders of magnitude within a few hours or days, resulting in several orders of magnitude fault probability variation in ICs during SPEs. This thesis introduces a comprehensive approach for designing a self-adaptive fault resilient multiprocessing system to overcome the static mitigation overhead issue. This work mainly addresses the following topics: (1) Design of on-chip radiation particle monitor for real-time radiation environment detection, (2) Investigation of space environment predictor, as support for solar particle events forecast, (3) Dynamic mode configuration in the resilient multiprocessing system. Therefore, according to detected and predicted in-flight space radiation conditions, the target system can be configured to use no mitigation or low-overhead mitigation during non-critical periods of time. The redundant resources can be used to improve system performance or save power. On the other hand, during increased radiation activity periods, such as SPEs, the mitigation methods can be dynamically configured appropriately depending on the real-time space radiation environment, resulting in higher system reliability. Thus, a dynamic trade-off in the target system between reliability, performance and power consumption in real-time can be achieved. All results of this work are evaluated in a highly reliable quad-core multiprocessing system that allows the self-adaptive setting of optimal radiation mitigation mechanisms during run-time. Proposed methods can serve as a basis for establishing a comprehensive self-adaptive resilient system design process. Successful implementation of the proposed design in the quad-core multiprocessor shows its application perspective also in the other designs.},
  language  = {en}
}
@article{SchaubWang2003,
  author    = {Schaub, Torsten H. and Wang, Kewen},
  title     = {A semantic framework for prefernce handling in answer set programming},
  year      = {2003},
  language  = {en}
}
@article{GoesselChakrabartyOcheretnijetal.2004,
  author    = {Goessel, Michael and Chakrabarty, Krishnendu and Ocheretnij, V. and Leininger, Andreas},
  title     = {A signature analysis technique for the identification of failing vectors with application to Scan-BIST},
  issn      = {0923-8174},
  year      = {2004},
  abstract  = {We present a new technique for uniquely identifying a single failing vector in an interval of test vectors. This technique is applicable to combinational circuits and for scan-BIST in sequential circuits with multiple scan chains. The proposed method relies on the linearity properties of the MISR and on the use of two test sequences, which are both applied to the circuit under test. The second test sequence is derived from the first in a straightforward manner and the same test pattern source is used for both test sequences. If an interval contains only a single failing vector, the algebraic analysis is guaranteed to identify it. We also show analytically that if an interval contains two failing vectors, the probability that this case is interpreted as one failing vector is very low. We present experimental results for the ISCAS benchmark circuits to demonstrate the use of the proposed method for identifying failing test vectors},
  language  = {en}
}
@article{BesnardSchaub1996,
  author    = {Besnard, Philippe and Schaub, Torsten H.},
  title     = {A simple signed system for paraconsistent reasoning},
  isbn      = {3-540-61630-6},
  year      = {1996},
  language  = {en}
}
@article{SeuringGoesselSogomonyan1998,
  author    = {Seuring, Markus and G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {A structural approach for space compaction for concurrent checking and BIST},
  year      = {1998},
  language  = {en}
}
@book{SeuringGoesselSogomonyan1997,
  author    = {Seuring, Markus and G{\"o}ssel, Michael and Sogomonyan, Egor S.},
  title     = {A structural approach for space compaction for concurrent checking and BIST},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {1997, 01},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ. Potsdam},
  address   = {Potsdam [u.a.]},
  issn      = {0946-7580},
  pages     = {19 S. : Ill.},
  year      = {1997},
  language  = {en}
}
@article{SeuringGoessel1999,
  author    = {Seuring, Markus and G{\"o}ssel, Michael},
  title     = {A structural approach for space compaction for sequential circuits},
  year      = {1999},
  language  = {en}
}
@book{SeuringGoessel1998,
  author    = {Seuring, Markus and G{\"o}ssel, Michael},
  title     = {A structural approach for space compaction for sequential circuits},
  series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  volume    = {1998, 05},
  journal   = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik},
  publisher = {Univ.},
  address   = {Potsdam},
  issn      = {0946-7580},
  pages     = {16 Bl. : graph. Darst.},
  year      = {1998},
  language  = {en}
}
@article{SeuringGoessel1999,
  author    = {Seuring, Markus and G{\"o}ssel, Michael},
  title     = {A structural method for output compaction of sequential automata implemented as circuits},
  year      = {1999},
  language  = {en}
}