@article{KreowskyStabernack2021,
  author    = {Kreowsky, Philipp and Stabernack, Christian Benno},
  title     = {A full-featured FPGA-based pipelined architecture for SIFT extraction},
  series = {IEEE access : practical research, open solutions / Institute of Electrical and Electronics Engineers},
  volume    = {9},
  journal   = {IEEE access : practical research, open solutions / Institute of Electrical and Electronics Engineers},
  publisher = {Inst. of Electr. and Electronics Engineers},
  address   = {New York, NY},
  issn      = {2169-3536},
  doi       = {10.1109/ACCESS.2021.3104387},
  pages     = {128564 -- 128573},
  year      = {2021},
  abstract  = {Image feature detection is a key task in computer vision. Scale Invariant Feature Transform (SIFT) is a prevalent and well known algorithm for robust feature detection. However, it is computationally demanding and software implementations are not applicable for real-time performance. In this paper, a versatile and pipelined hardware implementation is proposed, that is capable of computing keypoints and rotation invariant descriptors on-chip. All computations are performed in single precision floating-point format which makes it possible to implement the original algorithm with little alteration. Various rotation resolutions and filter kernel sizes are supported for images of any resolution up to ultra-high definition. For full high definition images, 84 fps can be processed. Ultra high definition images can be processed at 21 fps.},
  language  = {en}
}