@article{BreitenreiterAndjelkovićSchrapeetal.2022,
  author    = {Breitenreiter, Anselm and Andjelković, Marko and Schrape, Oliver and Krstić, Miloš},
  title     = {Fast error propagation probability estimates by answer set programming and approximate model counting},
  series = {IEEE Access},
  volume    = {10},
  journal   = {IEEE Access},
  publisher = {Inst. of Electr. and Electronics Engineers},
  address   = {Piscataway},
  issn      = {2169-3536},
  doi       = {10.1109/ACCESS.2022.3174564},
  pages     = {51814 -- 51825},
  year      = {2022},
  abstract  = {We present a method employing Answer Set Programming in combination with Approximate Model Counting for fast and accurate calculation of error propagation probabilities in digital circuits. By an efficient problem encoding, we achieve an input data format similar to a Verilog netlist so that extensive preprocessing is avoided. By a tight interconnection of our application with the underlying solver, we avoid iterating over fault sites and reduce calls to the solver. Several circuits were analyzed with varying numbers of considered cycles and different degrees of approximation. Our experiments show, that the runtime can be reduced by approximation by a factor of 91, whereas the error compared to the exact result is below 1\%.},
  language  = {en}
}
@article{LiBreitenreiterAndjelkovicetal.2020,
  author    = {Li, Yuanqing and Breitenreiter, Anselm and Andjelkovic, Marko and Chen, Junchao and Babic, Milan and Krstić, Miloš},
  title     = {Double cell upsets mitigation through triple modular redundancy},
  series = {Microelectronics Journal},
  volume    = {96},
  journal   = {Microelectronics Journal},
  publisher = {Elsevier},
  address   = {Oxford},
  issn      = {0026-2692},
  doi       = {10.1016/j.mejo.2019.104683},
  pages     = {8},
  year      = {2020},
  abstract  = {A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3\% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.},
  language  = {en}
}
@article{SchrapeAndjelkovicBreitenreiteretal.2021,
  author    = {Schrape, Oliver and Andjelkovic, Marko and Breitenreiter, Anselm and Zeidler, Steffen and Balashov, Alexey and Krstić, Miloš},
  title     = {Design and evaluation of radiation-hardened standard cell flip-flops},
  series = {IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers},
  volume    = {68},
  journal   = {IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers},
  number    = {11},
  publisher = {Inst. of Electr. and Electronics Engineers},
  address   = {New York, NY},
  issn      = {1549-8328},
  doi       = {10.1109/TCSI.2021.3109080},
  pages     = {4796 -- 4809},
  year      = {2021},
  abstract  = {Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant.},
  language  = {en}
}