@misc{Giese2017,
  author    = {Giese, Holger},
  title     = {Formal models and analysis for self-adaptive cyber-physical systems},
  series = {Lecture notes in computer science},
  volume    = {10231},
  journal   = {Lecture notes in computer science},
  editor    = {Kouchnarenko, Olga and Khosravi, Ramtin},
  publisher = {Springer},
  address   = {Cham},
  isbn      = {978-3-319-57666-4},
  issn      = {0302-9743},
  doi       = {10.1007/978-3-319-57666-4_1},
  pages     = {3 -- 9},
  year      = {2017},
  abstract  = {In this extended abstract, we will analyze the current challenges for the envisioned Self-Adaptive CPS. In addition, we will outline our results to approach these challenges with SMARTSOS [10] a generic approach based on extensions of graph transformation systems employing open and adaptive collaborations and models at runtime for trustworthy self-adaptation, self-organization, and evolution of the individual systems and the system-of-systems level taking the independent development, operation, management, and evolution of these systems into account.},
  language  = {en}
}
@misc{SaintDizierStede2017,
  author    = {Saint-Dizier, Patrick and Stede, Manfred},
  title     = {Foundations of the language of argumentation},
  series = {Argument \& computation},
  volume    = {8},
  journal   = {Argument \& computation},
  number    = {2 Special issue},
  publisher = {IOS Press},
  address   = {Amsterdam},
  issn      = {1946-2166},
  doi       = {10.3233/AAC-170018},
  pages     = {91 -- 93},
  year      = {2017},
  language  = {en}
}
@misc{FabianBaumannEhlertetal.2017,
  author    = {Fabian, Benjamin and Baumann, Annika and Ehlert, Mathias and Ververis, Vasilis and Ermakova, Tatiana},
  title     = {CORIA - Analyzing internet connectivity risks using network graphs},
  series = {2017 IEEE International Conference on Communications (ICC)},
  journal   = {2017 IEEE International Conference on Communications (ICC)},
  publisher = {IEEE},
  address   = {Piscataway},
  isbn      = {978-1-4673-8999-0},
  issn      = {1550-3607},
  doi       = {10.1109/ICC.2017.7996828},
  pages     = {6},
  year      = {2017},
  abstract  = {The Internet can be considered as the most important infrastructure for modern society and businesses. A loss of Internet connectivity has strong negative financial impacts for businesses and economies. Therefore, assessing Internet connectivity, in particular beyond their own premises and area of direct control, is of growing importance in the face of potential failures, accidents, and malicious attacks. This paper presents CORIA, a software framework for an easy analysis of connectivity risks based on large network graphs. It provides researchers, risk analysts, network managers and security consultants with a tool to assess an organization's connectivity and paths options through the Internet backbone, including a user-friendly and insightful visual representation of results. CORIA is flexibly extensible in terms of novel data sets, graph metrics, and risk scores that enable further use cases. The performance of CORIA is evaluated by several experiments on the Internet graph and further randomly generated networks.},
  language  = {en}
}
@misc{MuehlbauerSchroederSchoelzel2017,
  author    = {M{\"u}hlbauer, Felix and Schr{\"o}der, Lukas and Sch{\"o}lzel, Mario},
  title     = {On hardware-based fault-handling in dynamically scheduled processors},
  series = {20th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS) 2017},
  journal   = {20th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS) 2017},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-5386-0472-4},
  issn      = {2334-3133},
  doi       = {10.1109/DDECS.2017.7934572},
  pages     = {201 -- 206},
  year      = {2017},
  abstract  = {This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes the processor-architecture a very good candidate for applications with dynamically changing reliability requirements, e.g. for automotive applications. The paper reports the hardware-overhead for the extensions, and investigates the performance penalties introduced by the fail-safe and fault-tolerant mode. Furthermore, a comprehensive fault simulation was carried out in order to investigate the fault-coverage of the proposed approach.},
  language  = {en}
}
@misc{MuehlbauerSchroederSkoncejetal.2017,
  author    = {M{\"u}hlbauer, Felix and Schr{\"o}der, Lukas and Skoncej, Patryk and Sch{\"o}lzel, Mario},
  title     = {Handling manufacturing and aging faults with software-based techniques in tiny embedded systems},
  series = {18th IEEE Latin American Test Symposium (LATS 2017)},
  journal   = {18th IEEE Latin American Test Symposium (LATS 2017)},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-5386-0415-1},
  doi       = {10.1109/LATW.2017.7906756},
  pages     = {6},
  year      = {2017},
  abstract  = {Non-volatile memory area occupies a large portion of the area of a chip in an embedded system. Such memories are prone to manufacturing faults, retention faults, and aging faults. The paper presents a single software based technique that allows for handling all of these fault types in tiny embedded systems without the need for hardware support. This is beneficial for low-cost embedded systems with simple memory architectures. A software infrastructure and a flow are presented that demonstrate how the presented technique is used in general for fault handling right after manufacturing and in-the-field. Moreover, a full implementation is presented for a MSP430 microcontroller, along with a discussion of the performance, overhead, and reliability impacts.},
  language  = {en}
}