@article{BhattacharyaDimitrievGoessel2000, author = {Bhattacharya, M. K. and Dimitriev, Alexej and G{\"o}ssel, Michael}, title = {Zero-aliasing space compresion using a single periodic output and its application to testing of embedded}, year = {2000}, language = {en} } @article{DimitrievSaposhnikovSaposhnikovetal.1999, author = {Dimitriev, Alexej and Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael}, title = {Concurrent checking of sequential circuits by alternating inputs}, year = {1999}, language = {en} } @article{KuentzerKrstić2020, author = {Kuentzer, Felipe A. and Krstić, Miloš}, title = {Soft error detection and correction architecture for asynchronous bundled data designs}, series = {IEEE transactions on circuits and systems}, volume = {67}, journal = {IEEE transactions on circuits and systems}, number = {12}, publisher = {Institute of Electrical and Electronics Engineers}, address = {New York}, issn = {1549-8328}, doi = {10.1109/TCSI.2020.2998911}, pages = {4883 -- 4894}, year = {2020}, abstract = {In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6\% to 17.6\%, and increasing energy efficiency, which can be up to 6.5\%.}, language = {en} } @article{SaposhnikovOtscheretnijSaposhnikovetal.1998, author = {Saposhnikov, Vl. V. and Otscheretnij, Vitalij and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Design of Fault-Tolerant Circuits by self-dual Duplication}, year = {1998}, language = {en} } @article{MoschaninSaposhnikovSaposhnikovetal.1996, author = {Moschanin, Wladimir and Saposhnikov, Vl. V. and Saposhnikov, Va. V. and G{\"o}ssel, Michael}, title = {Synthesis of self-dual multi-output combinational circuits for on-line Teting}, year = {1996}, language = {en} } @article{SeuringGoesselSogomonyan1998, author = {Seuring, Markus and G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {Ein strukturelles Verfahren zur Kompaktierung von Schaltungsausgaben f{\"u}r online-Fehlererkennungen und Selbstests}, year = {1998}, language = {de} } @article{SogomonyanGoessel1996, author = {Sogomonyan, Egor S. and G{\"o}ssel, Michael}, title = {Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems}, year = {1996}, language = {en} } @article{MorosovGoesselHartje1999, author = {Morosov, Andrej and G{\"o}ssel, Michael and Hartje, Hendrik}, title = {Reduced area overhead of the input party for code-disjoint circuits}, year = {1999}, language = {en} } @article{SeuringGoessel1999, author = {Seuring, Markus and G{\"o}ssel, Michael}, title = {A structural method for output compaction of sequential automata implemented as circuits}, year = {1999}, language = {en} } @article{HlawiczkaGoesselSogomonyan1997, author = {Hlawiczka, A. and G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {A linear code-preserving signature analyzer COPMISR}, isbn = {0-8186-7810-0}, year = {1997}, language = {en} } @article{BogueGoesselJuergensenetal.1998, author = {Bogue, Ted and G{\"o}ssel, Michael and J{\"u}rgensen, Helmut and Zorian, Yervant}, title = {Built-in self-Test with an alternating output}, isbn = {0-8186-8359-7}, year = {1998}, language = {en} } @article{OtscheretnijGoesselSaposhnikovetal.1998, author = {Otscheretnij, Vitalij and G{\"o}ssel, Michael and Saposhnikov, Vl. V. and Saposhnikov, V. V.}, title = {Fault-tolerant self-dual circuits with error detection by parity- and group parity prediction}, year = {1998}, language = {en} } @article{SogomonyanSinghGoessel1998, author = {Sogomonyan, Egor S. and Singh, Adit D. and G{\"o}ssel, Michael}, title = {A multi-mode scannable memory element for high test application efficiency and delay testing}, year = {1998}, language = {en} } @article{DimitrievSaposhnikovGoesseletal.1997, author = {Dimitriev, Alexej and Saposhnikov, Vl. V. and G{\"o}ssel, Michael and Saposhnikov, V. V.}, title = {Self-dual duplication - a new method for on-line testing}, year = {1997}, language = {en} } @article{SaposhnikovMoshaninSaposhnikovetal.1997, author = {Saposhnikov, Vl. V. and Moshanin, Vl. and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Self-dual multi output combinational circuits with output data compaction}, year = {1997}, language = {en} } @article{GoesselSogomonyan1998, author = {G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {On-line Test auf der Grundlage eines die Parit{\"a}t erhaltenden Signaturanalysators}, year = {1998}, language = {de} } @article{MorosovSaposhnikovGoessel1998, author = {Morosov, Andrej and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Self-Checking circuits with unidiectionally independent outputs}, year = {1998}, language = {en} } @article{KrstićWeidlingPetrovicetal., author = {Krstić, Miloš and Weidling, Stefan and Petrovic, Vladimir and Sogomonyan, Egor S.}, title = {Enhanced architectures for soft error detection and correction in combinational and sequential circuits}, series = {Microelectronics Reliability}, volume = {56}, journal = {Microelectronics Reliability}, issn = {0026-2714}, pages = {212 -- 220}, abstract = {In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master-slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26-28\% lower than the TMR.}, language = {en} } @article{SchickBojahrHerzogetal.2014, author = {Schick, Daniel and Bojahr, Andre and Herzog, Marc and Shayduk, Roman and von Korff Schmising, Clemens and Bargheer, Matias}, title = {Udkm1Dsim-A simulation toolkit for 1D ultrafast dynamics in condensed matter}, series = {Computer physics communications : an international journal devoted to computational physics and computer programs in physics}, volume = {185}, journal = {Computer physics communications : an international journal devoted to computational physics and computer programs in physics}, number = {2}, publisher = {Elsevier}, address = {Amsterdam}, issn = {0010-4655}, doi = {10.1016/j.cpc.2013.10.009}, pages = {651 -- 660}, year = {2014}, abstract = {The UDKM1DSIM toolbox is a collection of MATLAB (MathWorks Inc.) classes and routines to simulate the structural dynamics and the according X-ray diffraction response in one-dimensional crystalline sample structures upon an arbitrary time-dependent external stimulus, e.g. an ultrashort laser pulse. The toolbox provides the capabilities to define arbitrary layered structures on the atomic level including a rich database of corresponding element-specific physical properties. The excitation of ultrafast dynamics is represented by an N-temperature model which is commonly applied for ultrafast optical excitations. Structural dynamics due to thermal stress are calculated by a linear-chain model of masses and springs. The resulting X-ray diffraction response is computed by dynamical X-ray theory. The UDKM1DSIM toolbox is highly modular and allows for introducing user-defined results at any step in the simulation procedure. Program summary Program title: udkm1Dsim Catalogue identifier: AERH_v1_0 Program summary URL: http://cpc.cs.qub.ac.uk/summaries/AERH_v1_0.html Licensing provisions: BSD No. of lines in distributed program, including test data, etc.: 130221 No. of bytes in distributed program, including test data, etc.: 2746036 Distribution format: tar.gz Programming language: Matlab (MathWorks Inc.). Computer: PC/Workstation. Operating system: Running Matlab installation required (tested on MS Win XP -7, Ubuntu Linux 11.04-13.04). Has the code been vectorized or parallelized?: Parallelization for dynamical XRD computations. Number of processors used: 1-12 for Matlab Parallel Computing Toolbox; 1 - infinity for Matlab Distributed Computing Toolbox External routines: Optional: Matlab Parallel Computing Toolbox, Matlab Distributed Computing Toolbox Required (included in the package): mtimesx Fast Matrix Multiply for Matlab by James Tursa, xml io tools by Jaroslaw Tuszynski, textprogressbar by Paul Proteus Nature of problem: Simulate the lattice dynamics of 1D crystalline sample structures due to an ultrafast excitation including thermal transport and compute the corresponding transient X-ray diffraction pattern. Solution method: Restrictions: The program is restricted to 1D sample structures and is further limited to longitudinal acoustic phonon modes and symmetrical X-ray diffraction geometries. Unusual features: The program is highly modular and allows the inclusion of user-defined inputs at any time of the simulation procedure. Running time: The running time is highly dependent on the number of unit cells in the sample structure and other simulation parameters such as time span or angular grid for X-ray diffraction computations. However, the example files are computed in approx. 1-5 min each on a 8 Core Processor with 16 GB RAM available.}, language = {en} } @article{CabalarFandinoFarinasdelCerro2021, author = {Cabalar, Pedro and Fandi{\~n}o, Jorge and Fari{\~n}as del Cerro, Luis}, title = {Splitting epistemic logic programs}, series = {Theory and practice of logic programming / publ. for the Association for Logic Programming}, volume = {21}, journal = {Theory and practice of logic programming / publ. for the Association for Logic Programming}, number = {3}, publisher = {Cambridge Univ. Press}, address = {Cambridge [u.a.]}, issn = {1471-0684}, doi = {10.1017/S1471068420000058}, pages = {296 -- 316}, year = {2021}, abstract = {Epistemic logic programs constitute an extension of the stable model semantics to deal with new constructs called subjective literals. Informally speaking, a subjective literal allows checking whether some objective literal is true in all or some stable models. As it can be imagined, the associated semantics has proved to be non-trivial, since the truth of subjective literals may interfere with the set of stable models it is supposed to query. As a consequence, no clear agreement has been reached and different semantic proposals have been made in the literature. Unfortunately, comparison among these proposals has been limited to a study of their effect on individual examples, rather than identifying general properties to be checked. In this paper, we propose an extension of the well-known splitting property for logic programs to the epistemic case. We formally define when an arbitrary semantics satisfies the epistemic splitting property and examine some of the consequences that can be derived from that, including its relation to conformant planning and to epistemic constraints. Interestingly, we prove (through counterexamples) that most of the existing approaches fail to fulfill the epistemic splitting property, except the original semantics proposed by Gelfond 1991 and a recent proposal by the authors, called Founded Autoepistemic Equilibrium Logic.}, language = {en} }