@article{BogueJuergensenGoessel1995, author = {Bogue, Ted and J{\"u}rgensen, Helmut and G{\"o}ssel, Michael}, title = {BIST with negligible aliasing through random cover circuits}, year = {1995}, language = {en} } @article{RabenaltRichterPoehletal.2012, author = {Rabenalt, Thomas and Richter, Michael and P{\"o}hl, Frank and G{\"o}ssel, Michael}, title = {Highly efficient test response compaction using a hierarchical x-masking technique}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, volume = {31}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, number = {6}, publisher = {Inst. of Electr. and Electronics Engineers}, address = {Piscataway}, issn = {0278-0070}, doi = {10.1109/TCAD.2011.2181847}, pages = {950 -- 957}, year = {2012}, abstract = {This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.}, language = {en} } @article{DugWeidlingSogomonyanetal.2020, author = {Dug, Mehmed and Weidling, Stefan and Sogomonyan, Egor and Jokic, Dejan and Krstić, Miloš}, title = {Full error detection and correction method applied on pipelined structure using two approaches}, series = {Journal of circuits, systems and computers}, volume = {29}, journal = {Journal of circuits, systems and computers}, number = {13}, publisher = {World Scientific}, address = {Singapore}, issn = {0218-1266}, doi = {10.1142/S0218126620502187}, pages = {15}, year = {2020}, abstract = {In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.}, language = {en} } @article{LiBreitenreiterAndjelkovicetal.2020, author = {Li, Yuanqing and Breitenreiter, Anselm and Andjelkovic, Marko and Chen, Junchao and Babic, Milan and Krstić, Miloš}, title = {Double cell upsets mitigation through triple modular redundancy}, series = {Microelectronics Journal}, volume = {96}, journal = {Microelectronics Journal}, publisher = {Elsevier}, address = {Oxford}, issn = {0026-2692}, doi = {10.1016/j.mejo.2019.104683}, pages = {8}, year = {2020}, abstract = {A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3\% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.}, language = {en} } @article{AndjelkovicSimevskiChenetal.2022, author = {Andjelkovic, Marko and Simevski, Aleksandar and Chen, Junchao and Schrape, Oliver and Stamenkovic, Zoran and Krstić, Miloš and Ilic, Stefan and Ristic, Goran and Jaksic, Aleksandar and Vasovic, Nikola and Duane, Russell and Palma, Alberto J. and Lallena, Antonio M. and Carvajal, Miguel A.}, title = {A design concept for radiation hardened RADFET readout system for space applications}, series = {Microprocessors and microsystems}, volume = {90}, journal = {Microprocessors and microsystems}, publisher = {Elsevier}, address = {Amsterdam}, issn = {0141-9331}, doi = {10.1016/j.micpro.2022.104486}, pages = {18}, year = {2022}, abstract = {Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET's response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions.}, language = {en} } @article{RisticIlicAndjelkovicetal.2022, author = {Ristic, Goran S. and Ilic, Stefan D. and Andjelkovic, Marko S. and Duane, Russell and Palma, Alberto J. and Lalena, Antonio M. and Krstić, Miloš and Jaksic, Aleksandar B.}, title = {Sensitivity and fading of irradiated RADFETs with different gate voltages}, series = {Nuclear Instruments and Methods in Physics Research Section A}, volume = {1029}, journal = {Nuclear Instruments and Methods in Physics Research Section A}, publisher = {Elsevier}, address = {Amsterdam}, issn = {0168-9002}, doi = {10.1016/j.nima.2022.166473}, pages = {7}, year = {2022}, abstract = {The radiation-sensitive field-effect transistors (RADFETs) with an oxide thickness of 400 nm are irradiated with gate voltages of 2, 4 and 6 V, and without gate voltage. A detailed analysis of the mechanisms responsible for the creation of traps during irradiation is performed. The creation of the traps in the oxide, near and at the silicon/silicon-dioxide (Si/SiO2) interface during irradiation is modelled very well. This modelling can also be used for other MOS transistors containing SiO2. The behaviour of radiation traps during postirradiation annealing is analysed, and the corresponding functions for their modelling are obtained. The switching traps (STs) do not have significant influence on threshold voltage shift, and two radiation-induced trap types fit the fixed traps (FTs) very well. The fading does not depend on the positive gate voltage applied during irradiation, but it is twice lower in case there is no gate voltage. A new dosimetric parameter, called the Golden Ratio (GR), is proposed, which represents the ratio between the threshold voltage shift after irradiation and fading after spontaneous annealing. This parameter can be useful for comparing MOS dosimeters.}, language = {en} } @article{HilscherBraunRichteretal.2009, author = {Hilscher, Martin and Braun, Michael and Richter, Michael and Leininger, Andreas and G{\"o}ssel, Michael}, title = {X-tolerant test data compaction with accelerated shift registers}, issn = {0923-8174}, doi = {10.1007/s10836-009-5107-5}, year = {2009}, abstract = {Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution.}, language = {en} } @article{GoesselSogomonyan1996, author = {G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {A new self-testing parity checker for ultra-reliable applications}, year = {1996}, language = {en} } @article{TavakoliAlirezazadehHedayatipouretal.2021, author = {Tavakoli, Hamad and Alirezazadeh, Pendar and Hedayatipour, Ava and Nasib, A. H. Banijamali and Landwehr, Niels}, title = {Leaf image-based classification of some common bean cultivars using discriminative convolutional neural networks}, series = {Computers and electronics in agriculture : COMPAG online ; an international journal}, volume = {181}, journal = {Computers and electronics in agriculture : COMPAG online ; an international journal}, publisher = {Elsevier}, address = {Amsterdam [u.a.]}, issn = {0168-1699}, doi = {10.1016/j.compag.2020.105935}, pages = {11}, year = {2021}, abstract = {In recent years, many efforts have been made to apply image processing techniques for plant leaf identification. However, categorizing leaf images at the cultivar/variety level, because of the very low inter-class variability, is still a challenging task. In this research, we propose an automatic discriminative method based on convolutional neural networks (CNNs) for classifying 12 different cultivars of common beans that belong to three various species. We show that employing advanced loss functions, such as Additive Angular Margin Loss and Large Margin Cosine Loss, instead of the standard softmax loss function for the classification can yield better discrimination between classes and thereby mitigate the problem of low inter-class variability. The method was evaluated by classifying species (level I), cultivars from the same species (level II), and cultivars from different species (level III), based on images from the leaf foreside and backside. The results indicate that the performance of the classification algorithm on the leaf backside image dataset is superior. The maximum mean classification accuracies of 95.86, 91.37 and 86.87\% were obtained at the levels I, II and III, respectively. The proposed method outperforms the previous relevant works and provides a reliable approach for plant cultivars identification.}, language = {en} } @article{GerberGoessel1994, author = {Gerber, Stefan and G{\"o}ssel, Michael}, title = {Detection of permanent faults of a floating point adder by pseudoduplication}, year = {1994}, language = {en} } @article{BhattacharyaDimitrievGoessel2000, author = {Bhattacharya, M. K. and Dimitriev, Alexej and G{\"o}ssel, Michael}, title = {Zero-aliasing space compresion using a single periodic output and its application to testing of embedded}, year = {2000}, language = {en} } @article{DimitrievSaposhnikovSaposhnikovetal.1999, author = {Dimitriev, Alexej and Saposhnikov, V. V. and Saposhnikov, Vl. V. and G{\"o}ssel, Michael}, title = {Concurrent checking of sequential circuits by alternating inputs}, year = {1999}, language = {en} } @article{KuentzerKrstić2020, author = {Kuentzer, Felipe A. and Krstić, Miloš}, title = {Soft error detection and correction architecture for asynchronous bundled data designs}, series = {IEEE transactions on circuits and systems}, volume = {67}, journal = {IEEE transactions on circuits and systems}, number = {12}, publisher = {Institute of Electrical and Electronics Engineers}, address = {New York}, issn = {1549-8328}, doi = {10.1109/TCSI.2020.2998911}, pages = {4883 -- 4894}, year = {2020}, abstract = {In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6\% to 17.6\%, and increasing energy efficiency, which can be up to 6.5\%.}, language = {en} } @article{SaposhnikovOtscheretnijSaposhnikovetal.1998, author = {Saposhnikov, Vl. V. and Otscheretnij, Vitalij and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Design of Fault-Tolerant Circuits by self-dual Duplication}, year = {1998}, language = {en} } @article{MoschaninSaposhnikovSaposhnikovetal.1996, author = {Moschanin, Wladimir and Saposhnikov, Vl. V. and Saposhnikov, Va. V. and G{\"o}ssel, Michael}, title = {Synthesis of self-dual multi-output combinational circuits for on-line Teting}, year = {1996}, language = {en} } @article{SeuringGoesselSogomonyan1998, author = {Seuring, Markus and G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {Ein strukturelles Verfahren zur Kompaktierung von Schaltungsausgaben f{\"u}r online-Fehlererkennungen und Selbstests}, year = {1998}, language = {de} } @article{SogomonyanGoessel1996, author = {Sogomonyan, Egor S. and G{\"o}ssel, Michael}, title = {Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems}, year = {1996}, language = {en} } @article{MorosovGoesselHartje1999, author = {Morosov, Andrej and G{\"o}ssel, Michael and Hartje, Hendrik}, title = {Reduced area overhead of the input party for code-disjoint circuits}, year = {1999}, language = {en} } @article{SeuringGoessel1999, author = {Seuring, Markus and G{\"o}ssel, Michael}, title = {A structural method for output compaction of sequential automata implemented as circuits}, year = {1999}, language = {en} } @article{HlawiczkaGoesselSogomonyan1997, author = {Hlawiczka, A. and G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {A linear code-preserving signature analyzer COPMISR}, isbn = {0-8186-7810-0}, year = {1997}, language = {en} } @article{BogueGoesselJuergensenetal.1998, author = {Bogue, Ted and G{\"o}ssel, Michael and J{\"u}rgensen, Helmut and Zorian, Yervant}, title = {Built-in self-Test with an alternating output}, isbn = {0-8186-8359-7}, year = {1998}, language = {en} } @article{OtscheretnijGoesselSaposhnikovetal.1998, author = {Otscheretnij, Vitalij and G{\"o}ssel, Michael and Saposhnikov, Vl. V. and Saposhnikov, V. V.}, title = {Fault-tolerant self-dual circuits with error detection by parity- and group parity prediction}, year = {1998}, language = {en} } @article{SogomonyanSinghGoessel1998, author = {Sogomonyan, Egor S. and Singh, Adit D. and G{\"o}ssel, Michael}, title = {A multi-mode scannable memory element for high test application efficiency and delay testing}, year = {1998}, language = {en} } @article{DimitrievSaposhnikovGoesseletal.1997, author = {Dimitriev, Alexej and Saposhnikov, Vl. V. and G{\"o}ssel, Michael and Saposhnikov, V. V.}, title = {Self-dual duplication - a new method for on-line testing}, year = {1997}, language = {en} } @article{SaposhnikovMoshaninSaposhnikovetal.1997, author = {Saposhnikov, Vl. V. and Moshanin, Vl. and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Self-dual multi output combinational circuits with output data compaction}, year = {1997}, language = {en} } @article{GoesselSogomonyan1998, author = {G{\"o}ssel, Michael and Sogomonyan, Egor S.}, title = {On-line Test auf der Grundlage eines die Parit{\"a}t erhaltenden Signaturanalysators}, year = {1998}, language = {de} } @article{MorosovSaposhnikovGoessel1998, author = {Morosov, Andrej and Saposhnikov, V. V. and G{\"o}ssel, Michael}, title = {Self-Checking circuits with unidiectionally independent outputs}, year = {1998}, language = {en} } @article{KrstićWeidlingPetrovicetal., author = {Krstić, Miloš and Weidling, Stefan and Petrovic, Vladimir and Sogomonyan, Egor S.}, title = {Enhanced architectures for soft error detection and correction in combinational and sequential circuits}, series = {Microelectronics Reliability}, volume = {56}, journal = {Microelectronics Reliability}, issn = {0026-2714}, pages = {212 -- 220}, abstract = {In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master-slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26-28\% lower than the TMR.}, language = {en} } @article{SchickBojahrHerzogetal.2014, author = {Schick, Daniel and Bojahr, Andre and Herzog, Marc and Shayduk, Roman and von Korff Schmising, Clemens and Bargheer, Matias}, title = {Udkm1Dsim-A simulation toolkit for 1D ultrafast dynamics in condensed matter}, series = {Computer physics communications : an international journal devoted to computational physics and computer programs in physics}, volume = {185}, journal = {Computer physics communications : an international journal devoted to computational physics and computer programs in physics}, number = {2}, publisher = {Elsevier}, address = {Amsterdam}, issn = {0010-4655}, doi = {10.1016/j.cpc.2013.10.009}, pages = {651 -- 660}, year = {2014}, abstract = {The UDKM1DSIM toolbox is a collection of MATLAB (MathWorks Inc.) classes and routines to simulate the structural dynamics and the according X-ray diffraction response in one-dimensional crystalline sample structures upon an arbitrary time-dependent external stimulus, e.g. an ultrashort laser pulse. The toolbox provides the capabilities to define arbitrary layered structures on the atomic level including a rich database of corresponding element-specific physical properties. The excitation of ultrafast dynamics is represented by an N-temperature model which is commonly applied for ultrafast optical excitations. Structural dynamics due to thermal stress are calculated by a linear-chain model of masses and springs. The resulting X-ray diffraction response is computed by dynamical X-ray theory. The UDKM1DSIM toolbox is highly modular and allows for introducing user-defined results at any step in the simulation procedure. Program summary Program title: udkm1Dsim Catalogue identifier: AERH_v1_0 Program summary URL: http://cpc.cs.qub.ac.uk/summaries/AERH_v1_0.html Licensing provisions: BSD No. of lines in distributed program, including test data, etc.: 130221 No. of bytes in distributed program, including test data, etc.: 2746036 Distribution format: tar.gz Programming language: Matlab (MathWorks Inc.). Computer: PC/Workstation. Operating system: Running Matlab installation required (tested on MS Win XP -7, Ubuntu Linux 11.04-13.04). Has the code been vectorized or parallelized?: Parallelization for dynamical XRD computations. Number of processors used: 1-12 for Matlab Parallel Computing Toolbox; 1 - infinity for Matlab Distributed Computing Toolbox External routines: Optional: Matlab Parallel Computing Toolbox, Matlab Distributed Computing Toolbox Required (included in the package): mtimesx Fast Matrix Multiply for Matlab by James Tursa, xml io tools by Jaroslaw Tuszynski, textprogressbar by Paul Proteus Nature of problem: Simulate the lattice dynamics of 1D crystalline sample structures due to an ultrafast excitation including thermal transport and compute the corresponding transient X-ray diffraction pattern. Solution method: Restrictions: The program is restricted to 1D sample structures and is further limited to longitudinal acoustic phonon modes and symmetrical X-ray diffraction geometries. Unusual features: The program is highly modular and allows the inclusion of user-defined inputs at any time of the simulation procedure. Running time: The running time is highly dependent on the number of unit cells in the sample structure and other simulation parameters such as time span or angular grid for X-ray diffraction computations. However, the example files are computed in approx. 1-5 min each on a 8 Core Processor with 16 GB RAM available.}, language = {en} } @article{CabalarFandinoFarinasdelCerro2021, author = {Cabalar, Pedro and Fandi{\~n}o, Jorge and Fari{\~n}as del Cerro, Luis}, title = {Splitting epistemic logic programs}, series = {Theory and practice of logic programming / publ. for the Association for Logic Programming}, volume = {21}, journal = {Theory and practice of logic programming / publ. for the Association for Logic Programming}, number = {3}, publisher = {Cambridge Univ. Press}, address = {Cambridge [u.a.]}, issn = {1471-0684}, doi = {10.1017/S1471068420000058}, pages = {296 -- 316}, year = {2021}, abstract = {Epistemic logic programs constitute an extension of the stable model semantics to deal with new constructs called subjective literals. Informally speaking, a subjective literal allows checking whether some objective literal is true in all or some stable models. As it can be imagined, the associated semantics has proved to be non-trivial, since the truth of subjective literals may interfere with the set of stable models it is supposed to query. As a consequence, no clear agreement has been reached and different semantic proposals have been made in the literature. Unfortunately, comparison among these proposals has been limited to a study of their effect on individual examples, rather than identifying general properties to be checked. In this paper, we propose an extension of the well-known splitting property for logic programs to the epistemic case. We formally define when an arbitrary semantics satisfies the epistemic splitting property and examine some of the consequences that can be derived from that, including its relation to conformant planning and to epistemic constraints. Interestingly, we prove (through counterexamples) that most of the existing approaches fail to fulfill the epistemic splitting property, except the original semantics proposed by Gelfond 1991 and a recent proposal by the authors, called Founded Autoepistemic Equilibrium Logic.}, language = {en} } @article{FandinoLifschitzLuehneetal.2020, author = {Fandi{\~n}o, Jorge and Lifschitz, Vladimir and L{\"u}hne, Patrick and Schaub, Torsten H.}, title = {Verifying tight logic programs with Anthem and Vampire}, series = {Theory and practice of logic programming}, volume = {20}, journal = {Theory and practice of logic programming}, number = {5}, publisher = {Cambridge Univ. Press}, address = {Cambridge [u.a.]}, issn = {1471-0684}, doi = {10.1017/S1471068420000344}, pages = {735 -- 750}, year = {2020}, abstract = {This paper continues the line of research aimed at investigating the relationship between logic programs and first-order theories. We extend the definition of program completion to programs with input and output in a subset of the input language of the ASP grounder gringo, study the relationship between stable models and completion in this context, and describe preliminary experiments with the use of two software tools, anthem and vampire, for verifying the correctness of programs with input and output. Proofs of theorems are based on a lemma that relates the semantics of programs studied in this paper to stable models of first-order formulas.}, language = {en} } @article{CabalarFandinoGareaetal.2020, author = {Cabalar, Pedro and Fandi{\~n}o, Jorge and Garea, Javier and Romero, Javier and Schaub, Torsten H.}, title = {Eclingo}, series = {Theory and practice of logic programming}, volume = {20}, journal = {Theory and practice of logic programming}, number = {6}, publisher = {Cambridge Univ. Press}, address = {New York}, issn = {1471-0684}, doi = {10.1017/S1471068420000228}, pages = {834 -- 847}, year = {2020}, abstract = {We describe eclingo, a solver for epistemic logic programs under Gelfond 1991 semantics built upon the Answer Set Programming system clingo. The input language of eclingo uses the syntax extension capabilities of clingo to define subjective literals that, as usual in epistemic logic programs, allow for checking the truth of a regular literal in all or in some of the answer sets of a program. The eclingo solving process follows a guess and check strategy. It first generates potential truth values for subjective literals and, in a second step, it checks the obtained result with respect to the cautious and brave consequences of the program. This process is implemented using the multi-shot functionalities of clingo. We have also implemented some optimisations, aiming at reducing the search space and, therefore, increasing eclingo 's efficiency in some scenarios. Finally, we compare the efficiency of eclingo with two state-of-the-art solvers for epistemic logic programs on a pair of benchmark scenarios and show that eclingo generally outperforms their obtained results.}, language = {en} } @article{RoessnerLuedemannBrustetal.2001, author = {Roessner, Ute and Luedemann, A. and Brust, D. and Fiehn, Oliver and Linke, Thomas and Willmitzer, Lothar and Fernie, Alisdair R.}, title = {Metabolic profiling allows comprehensive phenotyping of genetically or environmentally modified plant systems}, issn = {1040-4651}, year = {2001}, language = {en} } @article{CabalarFandinoSchaubetal.2019, author = {Cabalar, Pedro and Fandi{\~n}o, Jorge and Schaub, Torsten H. and Schellhorn, Sebastian}, title = {Gelfond-Zhang aggregates as propositional formulas}, series = {Artificial intelligence}, volume = {274}, journal = {Artificial intelligence}, publisher = {Elsevier}, address = {Amsterdam}, issn = {0004-3702}, doi = {10.1016/j.artint.2018.10.007}, pages = {26 -- 43}, year = {2019}, abstract = {Answer Set Programming (ASP) has become a popular and widespread paradigm for practical Knowledge Representation thanks to its expressiveness and the available enhancements of its input language. One of such enhancements is the use of aggregates, for which different semantic proposals have been made. In this paper, we show that any ASP aggregate interpreted under Gelfond and Zhang's (GZ) semantics can be replaced (under strong equivalence) by a propositional formula. Restricted to the original GZ syntax, the resulting formula is reducible to a disjunction of conjunctions of literals but the formulation is still applicable even when the syntax is extended to allow for arbitrary formulas (including nested aggregates) in the condition. Once GZ-aggregates are represented as formulas, we establish a formal comparison (in terms of the logic of Here-and-There) to Ferraris' (F) aggregates, which are defined by a different formula translation involving nested implications. In particular, we prove that if we replace an F-aggregate by a GZ-aggregate in a rule head, we do not lose answer sets (although more can be gained). This extends the previously known result that the opposite happens in rule bodies, i.e., replacing a GZ-aggregate by an F-aggregate in the body may yield more answer sets. Finally, we characterize a class of aggregates for which GZ- and F-semantics coincide.}, language = {en} } @article{AguadoCabalarFandinoetal.2019, author = {Aguado, Felicidad and Cabalar, Pedro and Fandi{\~n}o, Jorge and Pearce, David and Perez, Gilberto and Vidal, Concepcion}, title = {Forgetting auxiliary atoms in forks}, series = {Artificial intelligence}, volume = {275}, journal = {Artificial intelligence}, publisher = {Elsevier}, address = {Amsterdam}, issn = {0004-3702}, doi = {10.1016/j.artint.2019.07.005}, pages = {575 -- 601}, year = {2019}, abstract = {In this work we tackle the problem of checking strong equivalence of logic programs that may contain local auxiliary atoms, to be removed from their stable models and to be forbidden in any external context. We call this property projective strong equivalence (PSE). It has been recently proved that not any logic program containing auxiliary atoms can be reformulated, under PSE, as another logic program or formula without them - this is known as strongly persistent forgetting. In this paper, we introduce a conservative extension of Equilibrium Logic and its monotonic basis, the logic of Here-and-There, in which we deal with a new connective '|' we call fork. We provide a semantic characterisation of PSE for forks and use it to show that, in this extension, it is always possible to forget auxiliary atoms under strong persistence. We further define when the obtained fork is representable as a regular formula.}, language = {en} } @article{AguadoCabalarFandinoetal.2019, author = {Aguado, Felicidad and Cabalar, Pedro and Fandi{\~n}o, Jorge and Pearce, David and Perez, Gilberto and Vidal-Peracho, Concepcion}, title = {Revisiting Explicit Negation in Answer Set Programming}, series = {Theory and practice of logic programming}, volume = {19}, journal = {Theory and practice of logic programming}, number = {5-6}, publisher = {Cambridge Univ. Press}, address = {New York}, issn = {1471-0684}, doi = {10.1017/S1471068419000267}, pages = {908 -- 924}, year = {2019}, language = {en} }