@misc{MeinelSack2004, author = {Meinel, Christoph and Sack, Harald}, title = {WWW : Kommunikation, Internetworking, Web-Technologien}, publisher = {Springer}, address = {Berlin}, isbn = {3-540-44276-6}, issn = {1439-5428}, pages = {1179 S.}, year = {2004}, language = {de} } @misc{NeubauerHaubeltWankoetal.2018, author = {Neubauer, Kai and Haubelt, Christian and Wanko, Philipp and Schaub, Torsten H.}, title = {Utilizing quad-trees for efficient design space exploration with partial assignment evaluation}, series = {2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)}, journal = {2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)}, publisher = {IEEE}, address = {New York}, isbn = {978-1-5090-0602-1}, issn = {2153-6961}, doi = {10.1109/ASPDAC.2018.8297362}, pages = {434 -- 439}, year = {2018}, abstract = {Recently, it has been shown that constraint-based symbolic solving techniques offer an efficient way for deciding binding and routing options in order to obtain a feasible system level implementation. In combination with various background theories, a feasibility analysis of the resulting system may already be performed on partial solutions. That is, infeasible subsets of mapping and routing options can be pruned early in the decision process, which fastens the solving accordingly. However, allowing a proper design space exploration including multi-objective optimization also requires an efficient structure for storing and managing non-dominated solutions. In this work, we propose and study the usage of the Quad-Tree data structure in the context of partial assignment evaluation during system synthesis. Out experiments show that unnecessary dominance checks can be avoided, which indicates a preference of Quad-Trees over a commonly used list-based implementation for large combinatorial optimization problems.}, language = {en} } @misc{PatilHaiderPopeetal.2011, author = {Patil, Kaustubh R. and Haider, Peter and Pope, Phillip B. and Turnbaugh, Peter J. and Morrison, Mark and Scheffer, Tobias and McHardy, Alice C.}, title = {Taxonomic metagenome sequence assignment with structured output models}, series = {Nature methods : techniques for life scientists and chemists}, volume = {8}, journal = {Nature methods : techniques for life scientists and chemists}, number = {3}, publisher = {Nature Publ. Group}, address = {London}, issn = {1548-7091}, doi = {10.1038/nmeth0311-191}, pages = {191 -- 192}, year = {2011}, language = {en} } @misc{SchaubWoltran2018, author = {Schaub, Torsten H. and Woltran, Stefan}, title = {Special issue on answer set programming}, series = {K{\"u}nstliche Intelligenz}, volume = {32}, journal = {K{\"u}nstliche Intelligenz}, number = {2-3}, publisher = {Springer}, address = {Heidelberg}, issn = {0933-1875}, doi = {10.1007/s13218-018-0554-8}, pages = {101 -- 103}, year = {2018}, language = {en} } @misc{MarweckiBaudisch2018, author = {Marwecki, Sebastian and Baudisch, Patrick}, title = {Scenograph}, series = {UIST '18: Proceedings of the 31st Annual ACM Symposium on User Interface Software and Technology}, journal = {UIST '18: Proceedings of the 31st Annual ACM Symposium on User Interface Software and Technology}, publisher = {Association for Computing Machinery}, address = {New York}, isbn = {978-1-4503-5948-1}, doi = {10.1145/3242587.3242648}, pages = {511 -- 520}, year = {2018}, abstract = {When developing a real-walking virtual reality experience, designers generally create virtual locations to fit a specific tracking volume. Unfortunately, this prevents the resulting experience from running on a smaller or differently shaped tracking volume. To address this, we present a software system called Scenograph. The core of Scenograph is a tracking volume-independent representation of real-walking experiences. Scenograph instantiates the experience to a tracking volume of given size and shape by splitting the locations into smaller ones while maintaining narrative structure. In our user study, participants' ratings of realism decreased significantly when existing techniques were used to map a 25m2 experience to 9m2 and an L-shaped 8m2 tracking volume. In contrast, ratings did not differ when Scenograph was used to instantiate the experience.}, language = {en} } @misc{KrstićJentzsch2018, author = {Krstić, Miloš and Jentzsch, Anne-Kristin}, title = {Reliability, safety and security of the electronics in automated driving vehicles - joint lab lecturing approach}, series = {2018 12TH European Workshop on Microelectronics Education (EWME)}, journal = {2018 12TH European Workshop on Microelectronics Education (EWME)}, publisher = {IEEE}, address = {New York}, isbn = {978-1-5386-1157-9}, pages = {21 -- 22}, year = {2018}, abstract = {This paper proposes an education approach for master and bachelor students to enhance their skills in the area of reliability, safety and security of the electronic components in automated driving. The approach is based on the active synergetic work of research institutes, academia and industry in the frame of joint lab. As an example, the jointly organized summer school with the respective focus is organized and elaborated.}, language = {en} } @misc{BordihnNagyVaszil2018, author = {Bordihn, Henning and Nagy, Benedek and Vaszil, Gy{\"o}rgy}, title = {Preface: Non-classical models of automata and applications VIII}, series = {RAIRO-Theoretical informatics and appli and applications}, volume = {52}, journal = {RAIRO-Theoretical informatics and appli and applications}, number = {2-4}, publisher = {EDP Sciences}, address = {Les Ulis}, issn = {0988-3754}, doi = {10.1051/ita/2018019}, pages = {87 -- 88}, year = {2018}, language = {en} } @misc{StoepelSchubertMargariaSteffen2007, author = {St{\"o}pel, Christoph and Schubert, Wolfgang and Margaria-Steffen, Tiziana}, title = {Plug-ins und Dienste : Ans{\"a}tze zu Bew{\"a}ltigung zeitvarianter Gesch{\"a}ftsprozesse}, series = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, volume = {2007, 2}, journal = {Preprint / Universit{\"a}t Potsdam, Institut f{\"u}r Informatik}, publisher = {Univ.}, address = {Potsdam}, issn = {0946-7580}, pages = {14 S.}, year = {2007}, language = {de} } @misc{SahlmannSchwotzer2018, author = {Sahlmann, Kristina and Schwotzer, Thomas}, title = {Ontology-based virtual IoT devices for edge computing}, series = {Proceedings of the 8th International Conference on the Internet of Things}, journal = {Proceedings of the 8th International Conference on the Internet of Things}, publisher = {Association for Computing Machinery}, address = {New York}, isbn = {978-1-4503-6564-2}, doi = {10.1145/3277593.3277597}, pages = {1 -- 7}, year = {2018}, abstract = {An IoT network may consist of hundreds heterogeneous devices. Some of them may be constrained in terms of memory, power, processing and network capacity. Manual network and service management of IoT devices are challenging. We propose a usage of an ontology for the IoT device descriptions enabling automatic network management as well as service discovery and aggregation. Our IoT architecture approach ensures interoperability using existing standards, i.e. MQTT protocol and SemanticWeb technologies. We herein introduce virtual IoT devices and their semantic framework deployed at the edge of network. As a result, virtual devices are enabled to aggregate capabilities of IoT devices, derive new services by inference, delegate requests/responses and generate events. Furthermore, they can collect and pre-process sensor data. These tasks on the edge computing overcome the shortcomings of the cloud usage regarding siloization, network bandwidth, latency and speed. We validate our proposition by implementing a virtual device on a Raspberry Pi.}, language = {en} } @misc{MuehlbauerSchroederSchoelzel2017, author = {M{\"u}hlbauer, Felix and Schr{\"o}der, Lukas and Sch{\"o}lzel, Mario}, title = {On hardware-based fault-handling in dynamically scheduled processors}, series = {20th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS) 2017}, journal = {20th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS) 2017}, publisher = {IEEE}, address = {New York}, isbn = {978-1-5386-0472-4}, issn = {2334-3133}, doi = {10.1109/DDECS.2017.7934572}, pages = {201 -- 206}, year = {2017}, abstract = {This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes the processor-architecture a very good candidate for applications with dynamically changing reliability requirements, e.g. for automotive applications. The paper reports the hardware-overhead for the extensions, and investigates the performance penalties introduced by the fail-safe and fault-tolerant mode. Furthermore, a comprehensive fault simulation was carried out in order to investigate the fault-coverage of the proposed approach.}, language = {en} }