@misc{XenikoudakisAhmedHarrisetal.2020, author = {Xenikoudakis, Georgios and Ahmed, Mayeesha and Harris, Jacob Colt and Wadleigh, Rachel and Paijmans, Johanna L. A. and Hartmann, Stefanie and Barlow, Axel and Lerner, Heather and Hofreiter, Michael}, title = {Ancient DNA reveals twenty million years of aquatic life in beavers}, series = {Current biology : CB}, volume = {30}, journal = {Current biology : CB}, number = {3}, publisher = {Current Biology Ltd.}, address = {London}, issn = {0960-9822}, doi = {10.1016/j.cub.2019.12.041}, pages = {R110 -- R111}, year = {2020}, abstract = {Xenikoudakis et al. report a partial mitochondrial genome of the extinct giant beaver Castoroides and estimate the origin of aquatic behavior in beavers to approximately 20 million years. This time estimate coincides with the extinction of terrestrial beavers and raises the question whether the two events had a common cause.}, language = {en} } @misc{SchaepersNiemuellerLakemeyeretal.2018, author = {Sch{\"a}pers, Bj{\"o}rn and Niemueller, Tim and Lakemeyer, Gerhard and Gebser, Martin and Schaub, Torsten H.}, title = {ASP-Based Time-Bounded Planning for Logistics Robots}, series = {Twenty-Eighth International Conference on Automated Planning and Scheduling (ICAPS 2018)}, journal = {Twenty-Eighth International Conference on Automated Planning and Scheduling (ICAPS 2018)}, publisher = {ASSOC Association for the Advancement of Artificial Intelligence}, address = {Palo Alto}, issn = {2334-0835}, pages = {509 -- 517}, year = {2018}, abstract = {Manufacturing industries are undergoing a major paradigm shift towards more autonomy. Automated planning and scheduling then becomes a necessity. The Planning and Execution Competition for Logistics Robots in Simulation held at ICAPS is based on this scenario and provides an interesting testbed. However, the posed problem is challenging as also demonstrated by the somewhat weak results in 2017. The domain requires temporal reasoning and dealing with uncertainty. We propose a novel planning system based on Answer Set Programming and the Clingo solver to tackle these problems and incentivize robot cooperation. Our results show a significant performance improvement, both, in terms of lowering computational requirements and better game metrics.}, language = {en} } @misc{SchaubWoltran2018, author = {Schaub, Torsten H. and Woltran, Stefan}, title = {Special issue on answer set programming}, series = {K{\"u}nstliche Intelligenz}, volume = {32}, journal = {K{\"u}nstliche Intelligenz}, number = {2-3}, publisher = {Springer}, address = {Heidelberg}, issn = {0933-1875}, doi = {10.1007/s13218-018-0554-8}, pages = {101 -- 103}, year = {2018}, language = {en} } @misc{SaintDizierStede2017, author = {Saint-Dizier, Patrick and Stede, Manfred}, title = {Foundations of the language of argumentation}, series = {Argument \& computation}, volume = {8}, journal = {Argument \& computation}, number = {2 Special issue}, publisher = {IOS Press}, address = {Amsterdam}, issn = {1946-2166}, doi = {10.3233/AAC-170018}, pages = {91 -- 93}, year = {2017}, language = {en} } @misc{SahlmannSchwotzer2018, author = {Sahlmann, Kristina and Schwotzer, Thomas}, title = {Ontology-based virtual IoT devices for edge computing}, series = {Proceedings of the 8th International Conference on the Internet of Things}, journal = {Proceedings of the 8th International Conference on the Internet of Things}, publisher = {Association for Computing Machinery}, address = {New York}, isbn = {978-1-4503-6564-2}, doi = {10.1145/3277593.3277597}, pages = {1 -- 7}, year = {2018}, abstract = {An IoT network may consist of hundreds heterogeneous devices. Some of them may be constrained in terms of memory, power, processing and network capacity. Manual network and service management of IoT devices are challenging. We propose a usage of an ontology for the IoT device descriptions enabling automatic network management as well as service discovery and aggregation. Our IoT architecture approach ensures interoperability using existing standards, i.e. MQTT protocol and SemanticWeb technologies. We herein introduce virtual IoT devices and their semantic framework deployed at the edge of network. As a result, virtual devices are enabled to aggregate capabilities of IoT devices, derive new services by inference, delegate requests/responses and generate events. Furthermore, they can collect and pre-process sensor data. These tasks on the edge computing overcome the shortcomings of the cloud usage regarding siloization, network bandwidth, latency and speed. We validate our proposition by implementing a virtual device on a Raspberry Pi.}, language = {en} } @misc{Przybylla2019, author = {Przybylla, Mareen}, title = {Interactive objects in physical computing and their role in the learning process}, series = {Constructivist foundations}, volume = {14}, journal = {Constructivist foundations}, number = {3}, publisher = {Vrije Univ.}, address = {Bussels}, issn = {1782-348X}, pages = {264 -- 266}, year = {2019}, abstract = {The target article discusses the question of how educational makerspaces can become places supportive of knowledge construction. This question is too often neglected by people who run makerspaces, as they mostly explain how to use different tools and focus on the creation of a product. In makerspaces, often pupils also engage in physical computing activities and thus in the creation of interactive artifacts containing embedded systems, such as smart shoes or wristbands, plant monitoring systems or drink mixing machines. This offers the opportunity to reflect on teaching physical computing in computer science education, where similarly often the creation of the product is so strongly focused upon that the reflection of the learning process is pushed into the background.}, language = {en} } @misc{PatilHaiderPopeetal.2011, author = {Patil, Kaustubh R. and Haider, Peter and Pope, Phillip B. and Turnbaugh, Peter J. and Morrison, Mark and Scheffer, Tobias and McHardy, Alice C.}, title = {Taxonomic metagenome sequence assignment with structured output models}, series = {Nature methods : techniques for life scientists and chemists}, volume = {8}, journal = {Nature methods : techniques for life scientists and chemists}, number = {3}, publisher = {Nature Publ. Group}, address = {London}, issn = {1548-7091}, doi = {10.1038/nmeth0311-191}, pages = {191 -- 192}, year = {2011}, language = {en} } @misc{NeubauerHaubeltWankoetal.2018, author = {Neubauer, Kai and Haubelt, Christian and Wanko, Philipp and Schaub, Torsten H.}, title = {Utilizing quad-trees for efficient design space exploration with partial assignment evaluation}, series = {2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)}, journal = {2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)}, publisher = {IEEE}, address = {New York}, isbn = {978-1-5090-0602-1}, issn = {2153-6961}, doi = {10.1109/ASPDAC.2018.8297362}, pages = {434 -- 439}, year = {2018}, abstract = {Recently, it has been shown that constraint-based symbolic solving techniques offer an efficient way for deciding binding and routing options in order to obtain a feasible system level implementation. In combination with various background theories, a feasibility analysis of the resulting system may already be performed on partial solutions. That is, infeasible subsets of mapping and routing options can be pruned early in the decision process, which fastens the solving accordingly. However, allowing a proper design space exploration including multi-objective optimization also requires an efficient structure for storing and managing non-dominated solutions. In this work, we propose and study the usage of the Quad-Tree data structure in the context of partial assignment evaluation during system synthesis. Out experiments show that unnecessary dominance checks can be avoided, which indicates a preference of Quad-Trees over a commonly used list-based implementation for large combinatorial optimization problems.}, language = {en} } @misc{MuehlbauerSchroederSkoncejetal.2017, author = {M{\"u}hlbauer, Felix and Schr{\"o}der, Lukas and Skoncej, Patryk and Sch{\"o}lzel, Mario}, title = {Handling manufacturing and aging faults with software-based techniques in tiny embedded systems}, series = {18th IEEE Latin American Test Symposium (LATS 2017)}, journal = {18th IEEE Latin American Test Symposium (LATS 2017)}, publisher = {IEEE}, address = {New York}, isbn = {978-1-5386-0415-1}, doi = {10.1109/LATW.2017.7906756}, pages = {6}, year = {2017}, abstract = {Non-volatile memory area occupies a large portion of the area of a chip in an embedded system. Such memories are prone to manufacturing faults, retention faults, and aging faults. The paper presents a single software based technique that allows for handling all of these fault types in tiny embedded systems without the need for hardware support. This is beneficial for low-cost embedded systems with simple memory architectures. A software infrastructure and a flow are presented that demonstrate how the presented technique is used in general for fault handling right after manufacturing and in-the-field. Moreover, a full implementation is presented for a MSP430 microcontroller, along with a discussion of the performance, overhead, and reliability impacts.}, language = {en} } @misc{MuehlbauerSchroederSchoelzel2017, author = {M{\"u}hlbauer, Felix and Schr{\"o}der, Lukas and Sch{\"o}lzel, Mario}, title = {On hardware-based fault-handling in dynamically scheduled processors}, series = {20th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS) 2017}, journal = {20th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS) 2017}, publisher = {IEEE}, address = {New York}, isbn = {978-1-5386-0472-4}, issn = {2334-3133}, doi = {10.1109/DDECS.2017.7934572}, pages = {201 -- 206}, year = {2017}, abstract = {This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes the processor-architecture a very good candidate for applications with dynamically changing reliability requirements, e.g. for automotive applications. The paper reports the hardware-overhead for the extensions, and investigates the performance penalties introduced by the fail-safe and fault-tolerant mode. Furthermore, a comprehensive fault simulation was carried out in order to investigate the fault-coverage of the proposed approach.}, language = {en} }