@article{RabenaltGoesselLeininger2011,
  author    = {Rabenalt, Thomas and Goessel, Michael and Leininger, Andreas},
  title     = {Masking of X-Values by use of a hierarchically configurable register},
  series = {Journal of electronic testing : theory and applications},
  volume    = {27},
  journal   = {Journal of electronic testing : theory and applications},
  number    = {1},
  publisher = {Springer},
  address   = {Dordrecht},
  issn      = {0923-8174},
  doi       = {10.1007/s10836-010-5179-2},
  pages     = {31 -- 41},
  year      = {2011},
  abstract  = {In this paper we consider masking of unknowns (X-values) for VLSI circuits. We present a new hierarchical method of X-masking which is a major improvement of the method proposed in [4], called WIDE1. By the method proposed, the number of observable scan cells is optimized and data volume for X-masking can be significantly reduced in comparison to WIDEL This is demonstrated for three industrial designs. In cases where all X-values have to be masked the novel approach is especially efficient.},
  language  = {en}
}
@article{GoesselChakrabartyOcheretnijetal.2004,
  author    = {Goessel, Michael and Chakrabarty, Krishnendu and Ocheretnij, V. and Leininger, Andreas},
  title     = {A signature analysis technique for the identification of failing vectors with application to Scan-BIST},
  issn      = {0923-8174},
  year      = {2004},
  abstract  = {We present a new technique for uniquely identifying a single failing vector in an interval of test vectors. This technique is applicable to combinational circuits and for scan-BIST in sequential circuits with multiple scan chains. The proposed method relies on the linearity properties of the MISR and on the use of two test sequences, which are both applied to the circuit under test. The second test sequence is derived from the first in a straightforward manner and the same test pattern source is used for both test sequences. If an interval contains only a single failing vector, the algebraic analysis is guaranteed to identify it. We also show analytically that if an interval contains two failing vectors, the probability that this case is interpreted as one failing vector is very low. We present experimental results for the ISCAS benchmark circuits to demonstrate the use of the proposed method for identifying failing test vectors},
  language  = {en}
}
@article{GoesselMorozovSapozhnikovetal.2005,
  author    = {Goessel, Michael and Morozov, A. V. and Sapozhnikov, V. V. and Sapozhaikov, Vl. V.},
  title     = {Checking combinational circuits by the method of logic complement},
  issn      = {0005-1179},
  year      = {2005},
  abstract  = {Design of fully self-testing combinational circuits was considered. A theorem defining the conditions for guaranteed logic complement-based design of fully self-testing circuit was proved. Examples were presented},
  language  = {en}
}
@book{GoesselOcheretnySogomonyanetal.2008,
  author    = {Goessel, Michael and Ocheretny, Vitaly and Sogomonyan, Egor S. and Marienfeld, Daniel},
  title     = {New methods of concurrent checking},
  series = {Frontiers in electronic testing},
  volume    = {42},
  journal   = {Frontiers in electronic testing},
  publisher = {Springer},
  address   = {Dordrecht; Heidelberg},
  isbn      = {978-1-402-08419-5},
  doi       = {10.1007/978-1-4020-8420-1},
  pages     = {250 S.},
  year      = {2008},
  language  = {en}
}