@article{ZhangLideGrijsetal.2015,
  author    = {Zhang, Chaoli and Li, Chengyuan and de Grijs, Richard and Bekki, Kenji and Deng, Licai and Zaggia, Simone and Rubele, Stefano and Piatti, Andres E. and Cioni, Maria-Rosa L. and Emerson, Jim and For, Bi-Qing and Ripepi, Vincenzo and Marconi, Marcella and Ivanov, Valentin D. and Chen, Li},
  title     = {The vmc survey. XVIII. radial dependence of the Low-Mass, 0.55-0.82M(circle dot) stellar mass function in the galactic globular cluster 47 tucanae},
  series = {The astrophysical journal : an international review of spectroscopy and astronomical physics},
  volume    = {815},
  journal   = {The astrophysical journal : an international review of spectroscopy and astronomical physics},
  number    = {2},
  publisher = {IOP Publ. Ltd.},
  address   = {Bristol},
  issn      = {0004-637X},
  doi       = {10.1088/0004-637X/815/2/95},
  pages     = {9},
  year      = {2015},
  language  = {en}
}
@article{LiChenNofaletal.2018,
  author    = {Li, Yuanqing and Chen, Li and Nofal, Issam and Chen, Mo and Wang, Haibin and Liu, Rui and Chen, Qingyu and Krstić, Miloš and Shi, Shuting and Guo, Gang and Baeg, Sang H. and Wen, Shi-Jie and Wong, Richard},
  title     = {Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree},
  series = {Microelectronics reliability},
  volume    = {87},
  journal   = {Microelectronics reliability},
  publisher = {Elsevier},
  address   = {Oxford},
  issn      = {0026-2714},
  doi       = {10.1016/j.microrel.2018.05.016},
  pages     = {24 -- 32},
  year      = {2018},
  abstract  = {The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.},
  language  = {en}
}