@article{ChenLangeAndjelkovicetal.2020,
  author    = {Chen, Junchao and Lange, Thomas and Andjelkovic, Milos and Simevski, Aleksandar and Krstić, Miloš},
  title     = {Prediction of solar particle events with SRAM-based soft error rate monitor and supervised machine learning},
  series = {Microelectronics reliability},
  volume    = {114},
  journal   = {Microelectronics reliability},
  publisher = {Elsevier},
  address   = {Oxford},
  issn      = {0026-2714},
  doi       = {10.1016/j.microrel.2020.113799},
  pages     = {6},
  year      = {2020},
  abstract  = {This work introduces an embedded approach for the prediction of Solar Particle Events (SPEs) in space applications by combining the real-time Soft Error Rate (SER) measurement with SRAM-based detector and the offline trained machine learning model. The proposed approach is intended for the self-adaptive fault-tolerant multiprocessing systems employed in space applications. With respect to the state-of-the-art, our solution allows for predicting the SER 1 h in advance and fine-grained hourly tracking of SER variations during SPEs as well as under normal conditions. Therefore, the target system can activate the appropriate mechanisms for radiation hardening before the onset of high radiation levels. Based on the comparison of five different machine learning algorithms trained with the public space flux database, the preliminary results indicate that the best prediction accuracy is achieved with the recurrent neural network (RNN) with long short-term memory (LSTM).},
  language  = {en}
}
@misc{SchrapeBalashovSimevskietal.2018,
  author    = {Schrape, Oliver and Balashov, Alexey and Simevski, Aleksandar and Benito, Carlos and Krstić, Miloš},
  title     = {Master-Clone placement with individual clock tree implementation},
  series = {2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)},
  journal   = {2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-5386-7656-1},
  pages     = {4},
  year      = {2018},
  abstract  = {A hybrid design approach of the hierarchical physical implementation design flow is presented and demonstrated on a fault-tolerant low-power multiprocessor system. The proposed flow allows to implement selected submodules in parallel with contrary requirements such as identical placement and individual block implementation. The overall system contains four Leon2 cores and communicates via the Waterbear framework and supports Adaptive Voltage Scaling (AVS) functionality. Three of the processor core variants are derived from the first baseline reference core but implemented individually at block level based on their clock tree specification. The chip is prepared for space applications and designed with triple modular redundancy (TMR) for control parts. The low-power performance is enabled by contemporary power and clock management control. An ASIC is fabricated in a low-power 0.13 mu m BiCMOS technology process node.},
  language  = {en}
}
@article{FanStegmannSchrappeetal.,
  author    = {Fan, Xin and Stegmann, Mikkel B. and Schrappe, Oliver and Zeidler, Steffen and Jensen, Isac G. and Thorsen, Jannich and Bjerregaard, Tobias and Krstić, Miloš},
  title     = {Frequency-domain optimization of digital switching noise based on clock scheduling},
  series = {IEEE Transactions on Circuits and Systems I},
  volume    = {63},
  journal   = {IEEE Transactions on Circuits and Systems I},
  number    = {7},
  issn      = {1549-8328},
  doi       = {10.1109/TCSI.2016.2546118},
  pages     = {982 -- 993},
  abstract  = {The simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in terms of noise power, a two-phase clocking scheme is employed for system timing. Second, on-chip clock latencies are manipulated to target harmonic peaks in specific frequency bands for the spectral noise optimization. An automated design flow, which allows for noise optimization in user-defined application-specific frequency bands, is developed. The effectiveness of our design solution is validated by measurements of substrate noise and conductive EMI (electromagnetic interference) noise on a test chip, which consists of four wireless sensor node baseband processors each addressing a distinct clock-tree-synthesis strategy. Compared to the reference synchronous design, the proposed clock scheduling solution substantially reduces noise in the target GSM-850 band, i.e., by 11.1 dB on the substrate noise and 12.9 dB on the EMI noise, along with dramatic noise peak drops measured at the 50-MHz clock frequency.},
  language  = {en}
}