@article{SchrapeAndjelkovicBreitenreiteretal.2021, author = {Schrape, Oliver and Andjelkovic, Marko and Breitenreiter, Anselm and Zeidler, Steffen and Balashov, Alexey and Krstić, Miloš}, title = {Design and evaluation of radiation-hardened standard cell flip-flops}, series = {IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers}, volume = {68}, journal = {IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers}, number = {11}, publisher = {Inst. of Electr. and Electronics Engineers}, address = {New York, NY}, issn = {1549-8328}, doi = {10.1109/TCSI.2021.3109080}, pages = {4796 -- 4809}, year = {2021}, abstract = {Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant.}, language = {en} } @article{RisticIlicAndjelkovicetal.2022, author = {Ristic, Goran S. and Ilic, Stefan D. and Andjelkovic, Marko S. and Duane, Russell and Palma, Alberto J. and Lalena, Antonio M. and Krstić, Miloš and Jaksic, Aleksandar B.}, title = {Sensitivity and fading of irradiated RADFETs with different gate voltages}, series = {Nuclear Instruments and Methods in Physics Research Section A}, volume = {1029}, journal = {Nuclear Instruments and Methods in Physics Research Section A}, publisher = {Elsevier}, address = {Amsterdam}, issn = {0168-9002}, doi = {10.1016/j.nima.2022.166473}, pages = {7}, year = {2022}, abstract = {The radiation-sensitive field-effect transistors (RADFETs) with an oxide thickness of 400 nm are irradiated with gate voltages of 2, 4 and 6 V, and without gate voltage. A detailed analysis of the mechanisms responsible for the creation of traps during irradiation is performed. The creation of the traps in the oxide, near and at the silicon/silicon-dioxide (Si/SiO2) interface during irradiation is modelled very well. This modelling can also be used for other MOS transistors containing SiO2. The behaviour of radiation traps during postirradiation annealing is analysed, and the corresponding functions for their modelling are obtained. The switching traps (STs) do not have significant influence on threshold voltage shift, and two radiation-induced trap types fit the fixed traps (FTs) very well. The fading does not depend on the positive gate voltage applied during irradiation, but it is twice lower in case there is no gate voltage. A new dosimetric parameter, called the Golden Ratio (GR), is proposed, which represents the ratio between the threshold voltage shift after irradiation and fading after spontaneous annealing. This parameter can be useful for comparing MOS dosimeters.}, language = {en} } @article{LiChenNofaletal.2018, author = {Li, Yuanqing and Chen, Li and Nofal, Issam and Chen, Mo and Wang, Haibin and Liu, Rui and Chen, Qingyu and Krstić, Miloš and Shi, Shuting and Guo, Gang and Baeg, Sang H. and Wen, Shi-Jie and Wong, Richard}, title = {Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree}, series = {Microelectronics reliability}, volume = {87}, journal = {Microelectronics reliability}, publisher = {Elsevier}, address = {Oxford}, issn = {0026-2714}, doi = {10.1016/j.microrel.2018.05.016}, pages = {24 -- 32}, year = {2018}, abstract = {The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.}, language = {en} } @article{LiBreitenreiterAndjelkovicetal.2020, author = {Li, Yuanqing and Breitenreiter, Anselm and Andjelkovic, Marko and Chen, Junchao and Babic, Milan and Krstić, Miloš}, title = {Double cell upsets mitigation through triple modular redundancy}, series = {Microelectronics Journal}, volume = {96}, journal = {Microelectronics Journal}, publisher = {Elsevier}, address = {Oxford}, issn = {0026-2692}, doi = {10.1016/j.mejo.2019.104683}, pages = {8}, year = {2020}, abstract = {A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3\% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.}, language = {en} } @article{KuentzerKrstić2020, author = {Kuentzer, Felipe A. and Krstić, Miloš}, title = {Soft error detection and correction architecture for asynchronous bundled data designs}, series = {IEEE transactions on circuits and systems}, volume = {67}, journal = {IEEE transactions on circuits and systems}, number = {12}, publisher = {Institute of Electrical and Electronics Engineers}, address = {New York}, issn = {1549-8328}, doi = {10.1109/TCSI.2020.2998911}, pages = {4883 -- 4894}, year = {2020}, abstract = {In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6\% to 17.6\%, and increasing energy efficiency, which can be up to 6.5\%.}, language = {en} } @article{KrstićWeidlingPetrovicetal., author = {Krstić, Miloš and Weidling, Stefan and Petrovic, Vladimir and Sogomonyan, Egor S.}, title = {Enhanced architectures for soft error detection and correction in combinational and sequential circuits}, series = {Microelectronics Reliability}, volume = {56}, journal = {Microelectronics Reliability}, issn = {0026-2714}, pages = {212 -- 220}, abstract = {In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master-slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26-28\% lower than the TMR.}, language = {en} } @misc{KrstićJentzsch2018, author = {Krstić, Miloš and Jentzsch, Anne-Kristin}, title = {Reliability, safety and security of the electronics in automated driving vehicles - joint lab lecturing approach}, series = {2018 12TH European Workshop on Microelectronics Education (EWME)}, journal = {2018 12TH European Workshop on Microelectronics Education (EWME)}, publisher = {IEEE}, address = {New York}, isbn = {978-1-5386-1157-9}, pages = {21 -- 22}, year = {2018}, abstract = {This paper proposes an education approach for master and bachelor students to enhance their skills in the area of reliability, safety and security of the electronic components in automated driving. The approach is based on the active synergetic work of research institutes, academia and industry in the frame of joint lab. As an example, the jointly organized summer school with the respective focus is organized and elaborated.}, language = {en} } @article{DugWeidlingSogomonyanetal.2020, author = {Dug, Mehmed and Weidling, Stefan and Sogomonyan, Egor and Jokic, Dejan and Krstić, Miloš}, title = {Full error detection and correction method applied on pipelined structure using two approaches}, series = {Journal of circuits, systems and computers}, volume = {29}, journal = {Journal of circuits, systems and computers}, number = {13}, publisher = {World Scientific}, address = {Singapore}, issn = {0218-1266}, doi = {10.1142/S0218126620502187}, pages = {15}, year = {2020}, abstract = {In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.}, language = {en} } @article{ChenLangeAndjelkovicetal.2022, author = {Chen, Junchao and Lange, Thomas and Andjelkovic, Marko and Simevski, Aleksandar and Lu, Li and Krstić, Miloš}, title = {Solar particle event and single event upset prediction from SRAM-based monitor and supervised machine learning}, series = {IEEE transactions on emerging topics in computing / IEEE Computer Society, Institute of Electrical and Electronics Engineers}, volume = {10}, journal = {IEEE transactions on emerging topics in computing / IEEE Computer Society, Institute of Electrical and Electronics Engineers}, number = {2}, publisher = {Institute of Electrical and Electronics Engineers}, address = {[New York, NY]}, issn = {2168-6750}, doi = {10.1109/TETC.2022.3147376}, pages = {564 -- 580}, year = {2022}, abstract = {The intensity of cosmic radiation may differ over five orders of magnitude within a few hours or days during the Solar Particle Events (SPEs), thus increasing for several orders of magnitude the probability of Single Event Upsets (SEUs) in space-borne electronic systems. Therefore, it is vital to enable the early detection of the SEU rate changes in order to ensure timely activation of dynamic radiation hardening measures. In this paper, an embedded approach for the prediction of SPEs and SRAM SEU rate is presented. The proposed solution combines the real-time SRAM-based SEU monitor, the offline-trained machine learning model and online learning algorithm for the prediction. With respect to the state-of-the-art, our solution brings the following benefits: (1) Use of existing on-chip data storage SRAM as a particle detector, thus minimizing the hardware and power overhead, (2) Prediction of SRAM SEU rate one hour in advance, with the fine-grained hourly tracking of SEU variations during SPEs as well as under normal conditions, (3) Online optimization of the prediction model for enhancing the prediction accuracy during run-time, (4) Negligible cost of hardware accelerator design for the implementation of selected machine learning model and online learning algorithm. The proposed design is intended for a highly dependable and self-adaptive multiprocessing system employed in space applications, allowing to trigger the radiation mitigation mechanisms before the onset of high radiation levels.}, language = {en} } @article{BreitenreiterAndjelkovićSchrapeetal.2022, author = {Breitenreiter, Anselm and Andjelković, Marko and Schrape, Oliver and Krstić, Miloš}, title = {Fast error propagation probability estimates by answer set programming and approximate model counting}, series = {IEEE Access}, volume = {10}, journal = {IEEE Access}, publisher = {Inst. of Electr. and Electronics Engineers}, address = {Piscataway}, issn = {2169-3536}, doi = {10.1109/ACCESS.2022.3174564}, pages = {51814 -- 51825}, year = {2022}, abstract = {We present a method employing Answer Set Programming in combination with Approximate Model Counting for fast and accurate calculation of error propagation probabilities in digital circuits. By an efficient problem encoding, we achieve an input data format similar to a Verilog netlist so that extensive preprocessing is avoided. By a tight interconnection of our application with the underlying solver, we avoid iterating over fault sites and reduce calls to the solver. Several circuits were analyzed with varying numbers of considered cycles and different degrees of approximation. Our experiments show, that the runtime can be reduced by approximation by a factor of 91, whereas the error compared to the exact result is below 1\%.}, language = {en} } @article{AndjelkovićChenSimevskietal.2021, author = {Andjelković, Marko and Chen, Junchao and Simevski, Aleksandar and Schrape, Oliver and Krstić, Miloš and Kraemer, Rolf}, title = {Monitoring of particle count rate and LET variations with pulse stretching inverters}, series = {IEEE transactions on nuclear science : a publication of the IEEE Nuclear and Plasma Sciences Society}, volume = {68}, journal = {IEEE transactions on nuclear science : a publication of the IEEE Nuclear and Plasma Sciences Society}, number = {8}, publisher = {Institute of Electrical and Electronics Engineers}, address = {New York, NY}, issn = {0018-9499}, doi = {10.1109/TNS.2021.3076400}, pages = {1772 -- 1781}, year = {2021}, abstract = {This study investigates the use of pulse stretching (skew-sized) inverters for monitoring the variation of count rate and linear energy transfer (LET) of energetic particles. The basic particle detector is a cascade of two pulse stretching inverters, and the required sensing area is obtained by connecting up to 12 two-inverter cells in parallel and employing the required number of parallel arrays. The incident particles are detected as single-event transients (SETs), whereby the SET count rate denotes the particle count rate, while the SET pulsewidth distribution depicts the LET variations. The advantage of the proposed solution is the possibility to sense the LET variations using fully digital processing logic. SPICE simulations conducted on IHP's 130-nm CMOS technology have shown that the SET pulsewidth varies by approximately 550 ps over the LET range from 1 to 100 MeV center dot cm(2) center dot mg(-1). The proposed detector is intended for triggering the fault-tolerant mechanisms within a self-adaptive multiprocessing system employed in space. It can be implemented as a standalone detector or integrated in the same chip with the target system.}, language = {en} } @article{AndjelkovicSimevskiChenetal.2022, author = {Andjelkovic, Marko and Simevski, Aleksandar and Chen, Junchao and Schrape, Oliver and Stamenkovic, Zoran and Krstić, Miloš and Ilic, Stefan and Ristic, Goran and Jaksic, Aleksandar and Vasovic, Nikola and Duane, Russell and Palma, Alberto J. and Lallena, Antonio M. and Carvajal, Miguel A.}, title = {A design concept for radiation hardened RADFET readout system for space applications}, series = {Microprocessors and microsystems}, volume = {90}, journal = {Microprocessors and microsystems}, publisher = {Elsevier}, address = {Amsterdam}, issn = {0141-9331}, doi = {10.1016/j.micpro.2022.104486}, pages = {18}, year = {2022}, abstract = {Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET's response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions.}, language = {en} }