@misc{AndjelkovicBabicLietal.2019,
  author    = {Andjelkovic, Marko and Babic, Milan and Li, Yuanqing and Schrape, Oliver and Krstić, Miloš and Kraemer, Rolf},
  title     = {Use of decoupling cells for mitigation of SET effects in CMOS combinational gates},
  series = {2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)},
  journal   = {2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-5386-9562-3},
  doi       = {10.1109/ICECS.2018.8617996},
  pages     = {361 -- 364},
  year      = {2019},
  abstract  = {This paper investigates the applicability of CMOS decoupling cells for mitigating the Single Event Transient (SET) effects in standard combinational gates. The concept is based on the insertion of two decoupling cells between the gate's output and the power/ground terminals. To verify the proposed hardening approach, extensive SPICE simulations have been performed with standard combinational cells designed in IHP's 130 nm bulk CMOS technology. Obtained simulation results have shown that the insertion of decoupling cells results in the increase of the gate's critical charge, thus reducing the gate's soft error rate (SER). Moreover, the decoupling cells facilitate the suppression of SET pulses propagating through the gate. It has been shown that the decoupling cells may be a competitive alternative to gate upsizing and gate duplication for hardening the gates with lower critical charge and multiple (3 or 4) inputs, as well as for filtering the short SET pulses induced by low-LET particles.},
  language  = {en}
}
@misc{TalaSchrapeKrstićetal.2018,
  author    = {Tala, Mahdi and Schrape, Oliver and Krstić, Miloš and Bertozzi, Davide},
  title     = {Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip},
  series = {XXXIII Conference on Design of Circuits and Integrated Systems (DCIS)},
  journal   = {XXXIII Conference on Design of Circuits and Integrated Systems (DCIS)},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-7281-0171-2},
  issn      = {2471-6170},
  doi       = {10.1109/DCIS.2018.8681461},
  pages     = {6},
  year      = {2018},
  abstract  = {The relentless improvement of silicon photonics is making optical interconnects and networks appealing for use in miniaturized systems, where electrical interconnects cannot keep up with the growing levels of core integration due to bandwidth density and power efficiency limitations. At the same time, solutions such as 3D stacking or 2.5D integration open the door to a fully dedicated process optimization for the photonic die. However, an architecture-level integration challenge arises between the electronic network and the optical one in such tightly-integrated parallel systems. It consists of adapting signaling rates, matching the different levels of communication parallelism, handling cross-domain flow control, addressing re-synchronization concerns, and avoiding protocol-dependent deadlock. The associated energy and performance overhead may offset the inherent benefits of the emerging technology itself. This paper explores a hybrid CMOS-ECL bridge architecture between 3D-stacked technology-heterogeneous networks-on-chip (NoCs). The different ways of overcoming the serialization challenge (i.e., through an improvement of the signaling rate and/or through space-/wavelength division multiplexing options) give rise to a configuration space that the paper explores, in search for the most energy-efficient configuration for high-performance.},
  language  = {en}
}