@article{RabenaltGoesselLeininger2011,
  author    = {Rabenalt, Thomas and Goessel, Michael and Leininger, Andreas},
  title     = {Masking of X-Values by use of a hierarchically configurable register},
  series = {Journal of electronic testing : theory and applications},
  volume    = {27},
  journal   = {Journal of electronic testing : theory and applications},
  number    = {1},
  publisher = {Springer},
  address   = {Dordrecht},
  issn      = {0923-8174},
  doi       = {10.1007/s10836-010-5179-2},
  pages     = {31 -- 41},
  year      = {2011},
  abstract  = {In this paper we consider masking of unknowns (X-values) for VLSI circuits. We present a new hierarchical method of X-masking which is a major improvement of the method proposed in [4], called WIDE1. By the method proposed, the number of observable scan cells is optimized and data volume for X-masking can be significantly reduced in comparison to WIDEL This is demonstrated for three industrial designs. In cases where all X-values have to be masked the novel approach is especially efficient.},
  language  = {en}
}
@article{HilscherBraunRichteretal.2009,
  author    = {Hilscher, Martin and Braun, Michael and Richter, Michael and Leininger, Andreas and G{\"o}ssel, Michael},
  title     = {X-tolerant test data compaction with accelerated shift registers},
  issn      = {0923-8174},
  doi       = {10.1007/s10836-009-5107-5},
  year      = {2009},
  abstract  = {Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution.},
  language  = {en}
}
@article{GoesselChakrabartyOcheretnijetal.2004,
  author    = {Goessel, Michael and Chakrabarty, Krishnendu and Ocheretnij, V. and Leininger, Andreas},
  title     = {A signature analysis technique for the identification of failing vectors with application to Scan-BIST},
  issn      = {0923-8174},
  year      = {2004},
  abstract  = {We present a new technique for uniquely identifying a single failing vector in an interval of test vectors. This technique is applicable to combinational circuits and for scan-BIST in sequential circuits with multiple scan chains. The proposed method relies on the linearity properties of the MISR and on the use of two test sequences, which are both applied to the circuit under test. The second test sequence is derived from the first in a straightforward manner and the same test pattern source is used for both test sequences. If an interval contains only a single failing vector, the algebraic analysis is guaranteed to identify it. We also show analytically that if an interval contains two failing vectors, the probability that this case is interpreted as one failing vector is very low. We present experimental results for the ISCAS benchmark circuits to demonstrate the use of the proposed method for identifying failing test vectors},
  language  = {en}
}
@phdthesis{Leininger2006,
  author    = {Leininger, Andreas},
  title     = {New diagnosis and test methods with high compaction rates},
  publisher = {Mensch \& Buch Verl.},
  address   = {Berlin},
  isbn      = {3-86664-066-8},
  pages     = {IX, 98 S. : Ill., graph. Darst.},
  year      = {2006},
  language  = {en}
}