@article{LiBreitenreiterAndjelkovicetal.2020,
  author    = {Li, Yuanqing and Breitenreiter, Anselm and Andjelkovic, Marko and Chen, Junchao and Babic, Milan and Krstić, Miloš},
  title     = {Double cell upsets mitigation through triple modular redundancy},
  series = {Microelectronics Journal},
  volume    = {96},
  journal   = {Microelectronics Journal},
  publisher = {Elsevier},
  address   = {Oxford},
  issn      = {0026-2692},
  doi       = {10.1016/j.mejo.2019.104683},
  pages     = {8},
  year      = {2020},
  abstract  = {A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3\% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.},
  language  = {en}
}
@article{LiChenNofaletal.2018,
  author    = {Li, Yuanqing and Chen, Li and Nofal, Issam and Chen, Mo and Wang, Haibin and Liu, Rui and Chen, Qingyu and Krstić, Miloš and Shi, Shuting and Guo, Gang and Baeg, Sang H. and Wen, Shi-Jie and Wong, Richard},
  title     = {Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree},
  series = {Microelectronics reliability},
  volume    = {87},
  journal   = {Microelectronics reliability},
  publisher = {Elsevier},
  address   = {Oxford},
  issn      = {0026-2714},
  doi       = {10.1016/j.microrel.2018.05.016},
  pages     = {24 -- 32},
  year      = {2018},
  abstract  = {The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.},
  language  = {en}
}