@misc{TalaSchrapeKrstićetal.2018,
  author    = {Tala, Mahdi and Schrape, Oliver and Krstić, Miloš and Bertozzi, Davide},
  title     = {Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip},
  series = {XXXIII Conference on Design of Circuits and Integrated Systems (DCIS)},
  journal   = {XXXIII Conference on Design of Circuits and Integrated Systems (DCIS)},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-7281-0171-2},
  issn      = {2471-6170},
  doi       = {10.1109/DCIS.2018.8681461},
  pages     = {6},
  year      = {2018},
  abstract  = {The relentless improvement of silicon photonics is making optical interconnects and networks appealing for use in miniaturized systems, where electrical interconnects cannot keep up with the growing levels of core integration due to bandwidth density and power efficiency limitations. At the same time, solutions such as 3D stacking or 2.5D integration open the door to a fully dedicated process optimization for the photonic die. However, an architecture-level integration challenge arises between the electronic network and the optical one in such tightly-integrated parallel systems. It consists of adapting signaling rates, matching the different levels of communication parallelism, handling cross-domain flow control, addressing re-synchronization concerns, and avoiding protocol-dependent deadlock. The associated energy and performance overhead may offset the inherent benefits of the emerging technology itself. This paper explores a hybrid CMOS-ECL bridge architecture between 3D-stacked technology-heterogeneous networks-on-chip (NoCs). The different ways of overcoming the serialization challenge (i.e., through an improvement of the signaling rate and/or through space-/wavelength division multiplexing options) give rise to a configuration space that the paper explores, in search for the most energy-efficient configuration for high-performance.},
  language  = {en}
}
@misc{SchrapeBalashovSimevskietal.2018,
  author    = {Schrape, Oliver and Balashov, Alexey and Simevski, Aleksandar and Benito, Carlos and Krstić, Miloš},
  title     = {Master-Clone placement with individual clock tree implementation},
  series = {2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)},
  journal   = {2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-5386-7656-1},
  pages     = {4},
  year      = {2018},
  abstract  = {A hybrid design approach of the hierarchical physical implementation design flow is presented and demonstrated on a fault-tolerant low-power multiprocessor system. The proposed flow allows to implement selected submodules in parallel with contrary requirements such as identical placement and individual block implementation. The overall system contains four Leon2 cores and communicates via the Waterbear framework and supports Adaptive Voltage Scaling (AVS) functionality. Three of the processor core variants are derived from the first baseline reference core but implemented individually at block level based on their clock tree specification. The chip is prepared for space applications and designed with triple modular redundancy (TMR) for control parts. The low-power performance is enabled by contemporary power and clock management control. An ASIC is fabricated in a low-power 0.13 mu m BiCMOS technology process node.},
  language  = {en}
}
@article{LiChenNofaletal.2018,
  author    = {Li, Yuanqing and Chen, Li and Nofal, Issam and Chen, Mo and Wang, Haibin and Liu, Rui and Chen, Qingyu and Krstić, Miloš and Shi, Shuting and Guo, Gang and Baeg, Sang H. and Wen, Shi-Jie and Wong, Richard},
  title     = {Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree},
  series = {Microelectronics reliability},
  volume    = {87},
  journal   = {Microelectronics reliability},
  publisher = {Elsevier},
  address   = {Oxford},
  issn      = {0026-2714},
  doi       = {10.1016/j.microrel.2018.05.016},
  pages     = {24 -- 32},
  year      = {2018},
  abstract  = {The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.},
  language  = {en}
}
@misc{KrstićJentzsch2018,
  author    = {Krstić, Miloš and Jentzsch, Anne-Kristin},
  title     = {Reliability, safety and security of the electronics in automated driving vehicles - joint lab lecturing approach},
  series = {2018 12TH European Workshop on Microelectronics Education (EWME)},
  journal   = {2018 12TH European Workshop on Microelectronics Education (EWME)},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-5386-1157-9},
  pages     = {21 -- 22},
  year      = {2018},
  abstract  = {This paper proposes an education approach for master and bachelor students to enhance their skills in the area of reliability, safety and security of the electronic components in automated driving. The approach is based on the active synergetic work of research institutes, academia and industry in the frame of joint lab. As an example, the jointly organized summer school with the respective focus is organized and elaborated.},
  language  = {en}
}