TY  - GEN
A1  - Mühlbauer, Felix
A1  - Schröder, Lukas
A1  - Schölzel, Mario
T1  - On hardware-based fault-handling in dynamically scheduled processors
T2  - 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2017
N2  - This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes the processor-architecture a very good candidate for applications with dynamically changing reliability requirements, e.g. for automotive applications. The paper reports the hardware-overhead for the extensions, and investigates the performance penalties introduced by the fail-safe and fault-tolerant mode. Furthermore, a comprehensive fault simulation was carried out in order to investigate the fault-coverage of the proposed approach.
Y1  - 2017
UR  - https://publishup.uni-potsdam.de/frontdoor/index/index/docId/56734
SN  - 978-1-5386-0472-4
SN  - 2334-3133
SN  - 2473-2117
SP  - 201
EP  - 206
PB  - IEEE
CY  - New York
ER  -