TY  - JOUR
A1  - Kunz, Wolfgang
A1  - Reddy, S. M.
A1  - Subodh, M.
A1  - Pradhan, D. K.
T1  - Efficient logic verification in a synthesis environment
Y1  - 1996
UR  - https://publishup.uni-potsdam.de/frontdoor/index/index/docId/26277
ER  -